Enhancing signal fidelity during interpolation

Patent metadata

Field	Value
Publication number	US-12562942-B2
Application number	US-202418660174-A
Country	US
Kind code	B2
Filing date	May 9, 2024
Priority date	May 9, 2024
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

An apparatus is provided for processing a digital signal for a digital-to-analog converter (“DAC”). The apparatus includes a monitoring component configured to monitor a sequence of samples of the digital signal for a predetermined pattern of signal values. Upon determining that the sequence of samples does include the predetermined pattern of signal values, then samples in the sequence of samples that include the predetermined pattern of signal values are sent to the DAC. Noise is injected into an interpolation component, and the noise is withheld from an output of the DAC.

First claim

What is claimed:

1 . A computer-implemented method for processing a digital signal for a digital-to-analog converter (“DAC”), comprising:
sampling a sequence of the digital signal;
determining whether the sampled sequence includes a predetermined pattern of signal values;
upon determining that the sampled sequence does include the predetermined pattern of signal values:
sending samples of the sampled sequence including the predetermined pattern of signal values to the DAC;
injecting noise into an interpolation component; and
withholding the injected noise from an output of the DAC.

2 . The computer-implemented method of claim 1 , wherein the noise is generated by the interpolation component computing interpolation values and operative to tune samples not included in the samples of the sequence.

3 . The computer-implemented method of claim 2 , wherein the sequence of the digital signal is a first sequence of the digital signal, and the method further comprising:
sampling a second sequence of the digital signal; monitoring a predetermined number of samples of the second sequence for the predetermined pattern of signal values; and upon determining that the second sequence does not include the predetermined pattern of signal values, then switching to using the interpolation component to compute interpolation values for samples of the second sequence.

4 . The computer-implemented method of claim 3 , further comprising:
storing the tuning samples to a computer memory; and retrieving the stored tuning samples from the computer memory for computing interpolation values for the tuning samples.

5 . The computer-implemented method of claim 4 , wherein the tuning samples comprise a waveform.

6 . The computer-implemented method of claim 5 , wherein the tuning samples are operative to provide a predetermined computational load on the interpolation component.

7 . The computer-implemented method of claim 1 , wherein the noise comprises gating pseudorandom broadband noise in a data pattern signal to the interpolation component.

8 . The computer-implemented method of claim 7 , wherein the gating pseudorandom broadband noise comprises a waveform encapsulation marker in the data pattern signal.

9 . The computer-implemented method of claim 1 , wherein the noise comprises periodic noise correlated to a predetermined frequency restriction of the interpolation component.

10 . The computer-implemented method of claim 1 , further comprising transmitting the signal to control a qubit in a quantum computer.

11 . An apparatus for processing a digital signal for a digital-to-analog converter (“DAC”), comprising:
a monitoring component configured to:
monitor a sequence of samples of the digital signal for a predetermined pattern of signal values;
upon determining that the sequence of samples does include the predetermined pattern of signal values:
sending samples in the sequence of samples that include the predetermined pattern of signal values to the DAC;
injecting noise into an interpolation component; and
withholding the injected noise from an output of the DAC.

12 . The apparatus of claim 11 , wherein the injected noise is configured to match a power envelope of the interpolation component.

13 . The apparatus of claim 12 , wherein the injected noise is configured to hold electrical power consumption of the interpolation component substantially constant during operational and latency periods.

14 . The apparatus of claim 11 , further comprising a computer memory configured to store the injected noise comprising a sampled sequence of the signal.

15 . The apparatus of claim 11 , wherein the interpolation component is configured to compute the interpolation values for a predetermined number of the samples in the sequence of samples.

16 . The apparatus of claim 15 , wherein the predetermined number of samples in the sequence is less than or equal to a total number of samples in the sequence of samples.

17 . The apparatus of claim 11 , wherein the noise comprises gating pseudorandom broadband noise in a data pattern signal to the interpolation component.

18 . The apparatus of claim 17 , wherein the gating pseudorandom broadband noise comprises a waveform encapsulation marker in the data pattern signal.

19 . The apparatus of claim 11 , wherein the noise comprises periodic noise correlated to a predetermined frequency restriction of the interpolation component.

20 . A computer system for processing a digital signal for a digital-to-analog convertor (“DAC”), the computer system having a processor, a computer-readable memory, a computer-readable tangible storage device, and program instructions stored on the storage device for execution by a processor via the computer-readable memory, wherein the computer system is configured to perform a method, comprising:
sampling a sequence of the digital signal;
determining whether the sampled sequence includes a predetermined pattern of signal values;
upon determining that the sampled sequence does include the predetermined pattern of signal values:
sending samples of the sampled sequence that include the predetermined pattern of signal values to the DAC;
injecting noise into an interpolation component; and
withholding the injected noise from an output of the DAC.

Assignees

• IBM

Inventors

• Paulik George
• Betke Jarrett
• Carter Austin
• Escobar Kevin Daniel
• Lindquist Timothy
• Ramirez Daniel
• Snell Bryce
• Zettles Iv George Russell
• Ekman Jeremy T
• Willenborg Scott M
• Walther Matthew A
• Wolseth Alexander Jay

Classifications

• H04L25/06 Primary

  DC level restoring means; Bias distortion correction {; Decision circuits providing symbol by symbol detection} · CPC title