Information processing apparatus and information processing method, and computer program

Patent metadata

Field	Value
Publication number	US-12562831-B2
Application number	US-202118019373-A
Country	US
Kind code	B2
Filing date	Jul 2, 2021
Priority date	Aug 27, 2020
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

There is provided an information processing apparatus that processes information regarding network environment resistance when performing time synchronization of devices. The information processing apparatus includes a control unit that associates a boundary clock function retaining device having a boundary clock function with network environment resistance index information indicating resistance to a network environment related to time synchronization of the boundary clock function retaining device. The network environment resistance index information is information indicating accuracy of the time synchronization of the boundary clock function retaining device corresponding to network environment information indicating the network environment.

First claim

The invention claimed is:

1 . An information processing method, comprising
associating a boundary clock function retaining device having a boundary clock function with network environment resistance index information indicating resistance to a network environment related to time synchronization of the boundary clock function retaining device; and controlling the boundary clock function retaining device based on the associated network environment resistance index information, wherein the network environment resistance index information is determined based on measurement of at least one of a phase difference or a frequency shift of a synchronization signal on a side of the boundary clock function retaining device.

2 . A non-transitory computer-readable storage medium having embodied thereon a computer program, which when executed by a computer causes the computer to execute a method, the method comprising:
associating a boundary clock function retaining device having a boundary clock function with network environment resistance index information indicating resistance to a network environment related to time synchronization of the boundary clock function retaining device; and controlling the boundary clock function retaining device based on the associated network environment resistance index information, wherein the network environment resistance index information is determined based on measurement of at least one of a phase difference or a frequency shift of a synchronization signal on a side of the boundary clock function retaining device.

3 . An information processing apparatus comprising circuitry configured to
associate a boundary clock function retaining device having a boundary clock function with network environment resistance index information indicating resistance to a network environment related to time synchronization of the boundary clock function retaining device, and control the boundary clock function retaining device based on the associated network environment resistance index information,
wherein the network environment resistance index information is determined based on measurement of at least one of a phase difference or a frequency shift of a synchronization signal on a side of the boundary clock function retaining device.

4 . The information processing apparatus according to claim 3 ,
wherein the network environment resistance index information includes information indicating accuracy of the time synchronization of the boundary clock function retaining device corresponding to network environment information indicating the network environment.

5 . The information processing apparatus according to claim 3 ,
wherein the network environment resistance index information includes information indicating the network environment in a case where accuracy of the time synchronization of the boundary clock function retaining device is equal to or more than a predetermined value.

6 . The information processing apparatus according to claim 3 ,
wherein network environment information indicating the network environment includes network load information indicating strength of a network load related to the boundary clock function retaining device.

7 . The information processing apparatus according to claim 6 ,
wherein the network load information includes information generated based on at least one of packet transfer jitter information indicating a packet transfer jitter or packet transfer delay information indicating a packet transfer delay.

8 . The information processing apparatus according to claim 6 ,
wherein the network load information includes information generated based on packet transfer jitter information indicating a packet transfer jitter and packet transfer delay information indicating a packet transfer delay, and wherein the packet transfer jitter information has a higher contribution rate to the network load information than the packet transfer delay information.

9 . The information processing apparatus according to claim 3 ,
wherein network environment information indicating the network environment includes information indicating a number of hops related to the time synchronization of the boundary clock function retaining device.

10 . The information processing apparatus according to claim 3 ,
wherein the circuitry generates the network environment resistance index information.

11 . The information processing apparatus according to claim 3 ,
wherein the circuitry determines, from among a plurality of the boundary clock function retaining devices connected to a first network line, a first intra-network line master device that performs time synchronization with a second intra-network line device connected by a second network line different from the first network line based on the network environment resistance index information associated with each of the boundary clock function retaining devices.

12 . The information processing apparatus according to claim 11 ,
wherein the circuitry determines to turn off a boundary clock function corresponding to two ports of a precision time protocol (PTP) path among a plurality of ports included in a boundary clock function retaining passing device that has a boundary clock function and is passed through the PTP path connecting the second intra-network line device and the first intra-network line device that performs time synchronization with the second intra-network line device.

13 . The information processing apparatus according to claim 11 ,
wherein the circuitry is directly connected to the first intra-network line master device that performs time synchronization with the second intra-network line device, and wherein the circuitry is further configured to
perform time synchronization with the first intra-network line master device, and
determine a first intra-network line device having only one or two ports as a master device in a domain different from a domain of the second intra-network line device.

14 . The information processing apparatus according to claim 11 ,
wherein the circuitry determines a precision time protocol (PTP) path that connects the first intra-network line master device and a predetermined first intra-network line device connected by the first network line based on the network environment resistance index information associated with each of the plurality of the boundary clock function retaining devices.

15 . The information processing apparatus according to claim 14 ,
wherein the circuitry determines on or off of a boundary clock function corresponding to two ports of the PTP path among a plurality of ports included in a boundary clock function retaining passing device that has a boundary clock function and exists in the PTP path based on the network environment resistance index information associated with each of the plurality of the boundary clock function retaining devices.

16 . The information processing apparatus according to claim 14 ,
wherein the circuitry determines a PTP domain of a passing device and the predetermined first intra-network line device existing in the PTP path among the plurality of first intra-network line devices based on the PTP path.

17 . The information processing apparatus according to claim 11 ,
wherein the circuitry determines the first intra-network line master device in response to detecting that a system configuration of the first network line has been changed.

18 . The information processing apparatus according to claim 11 ,
wherein the circuitry determines the f

Assignees

• Sony Group Corp

Inventors

• Kosaka Yoshihiro
• Nakamura Hitoshi
• Ishikawa Yusuke

Classifications

• H04L43/0894

  Packet rate · CPC title

• H04L43/087

  Jitter · CPC title

• H04L43/0864

  Round trip delays · CPC title

• H04L43/0829

  Packet loss · CPC title

• H04J3/14

  Monitoring arrangements {(for SDH/SONET rings H04J3/085)} · CPC title