Command clock structure

Patent metadata

Field	Value
Publication number	US-12562214-B2
Application number	US-202318520175-A
Country	US
Kind code	B2
Filing date	Nov 27, 2023
Priority date	Dec 6, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

Methods, systems, and devices for command clock structure are described. A memory device may receive a command to determine a relationship (e.g., a phase relationship) between an external clock and an internally generated clock. In some examples, the memory device may execute the command and may report (e.g., to a host device) whether the command is successfully or unsuccessfully executed. The memory device may report the successful or unsuccessful execution of the command by driving one or more pins to a first value or a second value.

First claim

What is claimed is:

1 . A method, comprising:
generating, by a memory device, a first clock signal based at least in part on a second clock signal that is received by the memory device; receiving, by the memory device, a command based at least in part on generating the first clock signal; executing an operation to determine a phase of the first clock signal relative to the second clock signal based at least in part on receiving the command; and transmitting, via at least one pin of the memory device, signaling indicating that the operation to determine the phase of the first clock signal relative to the second clock signal was successfully executed.

2 . The method of claim 1 , wherein transmitting the signaling indicating that the operation was successfully executed comprises:
driving the at least one pin to a first value for a duration, wherein the duration comprises a plurality of cycles of the first clock signal.

3 . The method of claim 2 , further comprising:
driving the at least one pin to a second value for a second duration that precedes the duration, wherein the second duration is associated with an initialization phase of the memory device.

4 . The method of claim 1 , further comprising:
determining the phase of the first clock signal relative to the second clock signal based at least in part on executing the operation.

5 . The method of claim 4 , wherein the phase of the first clock signal is aligned with the phase of the second clock signal.

6 . The method of claim 4 , wherein the phase of the first clock signal is offset from the phase of the second clock signal.

7 . The method of claim 1 , further comprising:
initializing the memory device based at least in part on a host device changing a frequency, the host device changing a voltage, the memory device performing a self-refresh operation, the memory device changing power states, or a combination thereof, wherein the command is received based at least in part on initializing the memory device.

8 . The method of claim 1 , further comprising:
receiving, by the memory device, a second command after transmitting the signaling indicating that the operation was successfully executed, the second command for determining the phase of the first clock signal relative to the second clock signal; attempting to execute a second operation based at least in part on receiving the second command; and transmitting, via the at least one pin of the memory device, second signaling indicating that the second operation was unsuccessfully executed based at least in part on attempting to execute the second command.

9 . The method of claim 8 , further comprising:
receiving, by the memory device, a third command based at least in part on transmitting the second signaling; executing a third operation to determine the phase of the first clock signal relative to the second clock signal based at least in part on receiving the third command; and transmitting, via the at least one pin of the memory device, third signaling indicating that the third operation was successfully executed to determine the phase of the first clock signal relative to the second clock signal.

10 . The method of claim 1 , wherein a frequency of the first clock signal is different than a frequency of the second clock signal.

11 . The method of claim 1 , wherein the first clock signal is internal to the memory device.

12 . The method of claim 1 , wherein the command comprises a command start point command.

13 . An apparatus, comprising:
a controller associated with a memory device comprising at least one pin, wherein the controller is configured to cause the apparatus to:
generate a first clock signal based at least in part on a second clock signal that is received by the memory device;
receive a command based at least in part on generating the first clock signal;
execute an operation to determine a phase of the first clock signal relative to the second clock signal based at least in part on receiving the command; and
transmit, via the at least one pin of the memory device, signaling indicating that the operation to determine the phase of the first clock signal relative to the second clock signal was successfully executed.

14 . The apparatus of claim 13 , wherein to transmit the signaling indicating that the operation was successfully executed, the controller is configured to cause the apparatus to:
drive the at least one pin to a first value for a duration, wherein the duration comprises a plurality of cycles of the first clock signal.

15 . The apparatus of claim 14 , wherein the controller is further configured to cause the apparatus to:
drive the at least one pin to a second value for a second duration that precedes the duration, wherein the second duration is associated with an initialization phase of the memory device.

16 . The apparatus of claim 13 , wherein the controller is further configured to cause the apparatus to:
determine the phase of the first clock signal relative to the second clock signal based at least in part on executing the operation.

17 . The apparatus of claim 16 , wherein the phase of the first clock signal is aligned with the phase of the second clock signal.

18 . The apparatus of claim 16 , wherein the phase of the first clock signal is offset from the phase of the second clock signal.

19 . The apparatus of claim 13 , wherein the controller is further configured to cause the apparatus to:
initialize the memory device based at least in part on a host device changing a frequency, the host device changing a voltage, the memory device performing a self-refresh operation, the memory device changing power states, or a combination thereof, wherein the command is received based at least in part on initializing the memory device.

20 . A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to:
generate, by a memory device, a first clock signal based at least in part on a second clock signal that is received by the memory device; receive, by the memory device, a command based at least in part on generating the first clock signal; execute an operation to determine a phase of the first clock signal relative to the second clock signal based at least in part on receiving the command; and transmit, via at least one pin of the memory device, signaling indicating that the operation to determine the phase of the first clock signal relative to the second clock signal was successfully executed.

Assignees

• Micron Technology Inc

Inventors

• Brox Martin
• Hein Thomas
• Vitale Filippo

Classifications

• G11C11/40615

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G11C11/4072 Primary

  Circuits for initialization, powering up or down, clearing memory or presetting · CPC title

• G11C11/4076 Primary

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title