Panel design to improve accurate defect location report

Patent metadata

Field	Value
Publication number	US-12561782-B2
Application number	US-202217955212-A
Country	US
Kind code	B2
Filing date	Sep 28, 2022
Priority date	Nov 17, 2021
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

An array checker (AC) is described. The array checker may include software configured to implement a method. By implementing the method, the array checker may detect a location of a defect and then compensate for a shift in the defect. In particular, the method may include generating one or more reference lines in a panel. The reference lines may include a location which is known prior to generating an image of the panel. The array checker may then capture an image of the panel. The image may be captured by voltage imaging. The image may include the defect and the one or more reference lines. The method may then include calculating an offset of the reference line from the known location. The offset may then be applied to the defect location for compensating the shift in the defect.

First claim

What is claimed:

1 . A method comprising:
activating one or more reference lines in an active area of a panel, wherein the one or more reference lines include a known reference line location in the active area; generating an image of at least a portion of the panel; detecting, in the image, a defect location of a defect in the active area and a reference line location of the one or more reference lines; determining an offset between the reference line location and the known reference line location, wherein the offset corresponds to a shift in the defect location; and determining a compensated defect location of the defect based on the defect location and the offset, wherein the defect is in an active segment of the panel, wherein the active segment has a width of at least 30 micrometers.

2 . The method of claim 1 , wherein the one or more reference lines are activated by switching one or more switches coupled to one of a gate line or a data line of the panel.

3 . The method of claim 1 , wherein the image is generated by voltage imaging using an array checker, wherein the voltage imaging comprises capacitively coupling an electro-optic modulator of the array checker to the panel, wherein the electro-optic modulator is locally opaque to illumination above the defect and the one or more reference lines when the electro-optic modulator is capacitively coupled to the panel, wherein the electro-optic modulator being locally opaque causes the electro-optic modulator to prevent the illumination from passing through to and reflect from the panel, wherein a detector of the array checker generates the image based on the illumination.

4 . The method of claim 1 , further comprising repairing the defect at the compensated defect location.

5 . The method of claim 4 , wherein a thin-film transistor array repair tool repairs the defect at the compensated defect location.

6 . An array checker including:
an illumination source configured to generate illumination; a stage for securing a panel; an electro-optic modulator disposed in a path of the illumination and separated from the panel by an airgap; a detector configured to generate an image of at least a portion of the panel; and one or more processors configured to execute program instructions maintained on a memory medium causing the one or more processors to:
activate one or more reference lines in an active area of the panel, wherein the one or more reference lines include a known reference line location in the active area;
generate the image of at least the portion of the panel;
detect, in the image, a defect location of a defect in the active area and a reference line location of the one or more reference lines;
determine an offset between the reference line location and the known reference line location, wherein the offset corresponds to a shift in the defect location; and
determine a compensated defect location of the defect based on the defect location and the offset, wherein the defect is in an active segment of the panel, wherein the active segment has a width of at least 30 micrometers.

7 . The array checker of claim 6 , wherein the array checker is configured to couple to one or more pads of the panel; wherein the array checker causes the one or more reference lines to activate by providing a control signal to one or more switches of the panel by way of the one or more pads, wherein the switches are coupled to one of a gate line of the panel or a data line of the panel.

8 . The array checker of claim 6 , wherein the electro-optic modulator is configured to capacitively couple to the panel; wherein the electro-optic modulator is locally opaque to the illumination above the defect and the one or more reference lines when the electro-optic modulator is capacitively coupled to the panel; wherein the electro-optic modulator being locally opaque causes the electro-optic modulator to prevent the illumination from passing through to and reflect from the panel.

9 . An imaging system comprising:
a panel including an active area, a plurality of gate lines, and a plurality of data lines, wherein the active area includes a plurality of active segments; and an array checker comprising:
an illumination source configured to generate illumination;
a stage for the panel;
an electro-optic modulator disposed in a path of the illumination and separated from the panel by an airgap;
a detector configured to generate an image of at least a portion of the panel; and
one or more processors configured to execute program instructions maintained on a memory medium causing the one or more processors to:
activate one or more reference lines in the active area of the panel, wherein the one or more reference lines include a known reference line location in the active area;
generate the image of at least the portion of the panel;
detect, in the image, a defect location of a defect in the active area and a reference line location of the one or more reference lines;
determine an offset between the reference line location and the known reference line location, wherein the offset corresponds to a shift in the defect location; and
determine a compensated defect location of the defect based on the defect location and the offset, wherein the defect is in an active segment of the panel, wherein the active segment has a width of at least 30 micrometers.

10 . The imaging system of claim 9 , wherein the panel includes one or more switches; wherein the one or more switches are coupled to one of a gate line of the plurality of gate lines or a data line of the plurality of data lines.

11 . The imaging system of claim 1 , wherein the panel includes a signal line coupling the one or more switches to one or more pads; wherein the array checker is coupled to the one or more pads; wherein the array checker causes the one or more reference lines to activate by providing a control signal to the one or more switches of the panel by way of the pad.

12 . The imaging system of claim 11 , wherein the one or more switches are coupled to one of the gate line or the data line outside of the active area; wherein the gate line is coupled to a row of active segments of the active area; wherein the data line is coupled to a column of active segments of the active area.

13 . The imaging system of claim 12 , wherein the one or more switches includes at least one switch coupled to the gate line for generating a horizontal reference line.

14 . The imaging system of claim 12 , wherein the one or more switches includes at least one switch coupled to the data line for generating a vertical reference line.

15 . The imaging system of claim 12 , wherein the one or more switches includes a first switch coupled to the gate line for generating a horizontal reference line; wherein the one or more switches includes a second switch coupled to the data line for generating a vertical reference line.

16 . The imaging system of claim 9 , wherein the panel is a liquid-crystal display panel including a thin-film transistor backplane.

17 . The imaging system of claim 16 , wherein the liquid-crystal display panel does not include a liquid crystal layer when the array checker generates the image.

18 . The imaging system of claim 9 , wherein the electro-optic modulator is configured to capacitively couple to the panel; wherein the electro-optic modulator is locally opaque to the illumination above the defect and the one or more reference lines when the electro-optic modulator is capacitively coupled to the panel; wherein the electro-optic

Assignees

• Orbotech Ltd

Inventors

• Chen nai-wei
• Chen Yueh-Nan
• Lai Chih-Chang
• Lee Gwan Sub
• Lee Jongho

Classifications

• G06T7/73

  using feature-based methods · CPC title

• G09G2330/12

  Test circuits or failure detection circuits included in a display system, as permanent part thereof · CPC title

• G09G2320/0693

  Calibration of display systems · CPC title

• G09G2330/10

  Dealing with defective pixels · CPC title

• G09G2300/043

  Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver · CPC title