Node prefetching in a wide BVH traversal with a stack

Patent metadata

Field	Value
Publication number	US-12561753-B2
Application number	US-202217699059-A
Country	US
Kind code	B2
Filing date	Mar 18, 2022
Priority date	Mar 18, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

Apparatus and method for prefetching node data. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to manage active ray tracing stack allocations within a traversal stack; and stack management hardware logic to issue a prefetch operation comprising an indication of bounding volume hierarchy (BVH) node data to be prefetched and an indication of a cache level, wherein responsive to performing the prefetch operation, the BVH node data is to be prefetched to the indicated cache level.

First claim

What is claimed is:

1 . An apparatus comprising:
ray tracing acceleration hardware to manage active ray tracing stack allocations within a traversal stack; and stack management hardware logic to issue a prefetch operation comprising an indication of bounding volume hierarchy (BVH) node data to be prefetched to perform ray tracing and an indication of a cache level, wherein responsive to performing the prefetch operation, the BVH node data is to be prefetched to the indicated cache level to be accessed by the ray tracing acceleration hardware to perform the ray tracing, wherein the prefetch operation is to identify a plurality of elements of the traversal stack, and wherein the stack management hardware logic is to identify the plurality of elements as a top-most elements of the traversal stack.

2 . The apparatus of claim 1 wherein the stack management hardware logic is to identify a plurality of elements as elements below one or more top-most elements of the traversal stack.

3 . The apparatus of claim 2 wherein the stack management hardware logic is to identify the plurality of elements by anticipating when the plurality of elements are to be accessed by the ray tracing acceleration hardware.

4 . The apparatus of claim 1 further comprising:
a cache subsystem comprising a hierarchy of cache levels, wherein the cache level identified by the prefetch operation comprises one of the cache levels in the hierarchy of cache levels.

5 . The apparatus of claim 4 wherein the cache level identified by the prefetch operation comprises one of an L2 cache, an L1 cache, and an L0 cache.

6 . The apparatus of claim 1 wherein the stack management hardware logic is to mark one or more entries of the traversal stack to indicate that the associated BVH node data has been prefetched.

7 . A method comprising:
managing, by ray tracing acceleration hardware, active ray tracing stack allocations within a traversal stack; and performing, by stack management hardware logic, a prefetch operation comprising an indication of bounding volume hierarchy (BVH) node data to be prefetched to perform ray tracing and an indication of a cache level, wherein responsive to performing the prefetch operation, the BVH node data is to be prefetched to the indicated cache level to be accessed by the ray tracing acceleration hardware to perform the ray tracing, wherein a plurality of elements are identified as elements below one or more top-most elements of the traversal stack.

8 . The method of claim 7 wherein the prefetch operation is to identify a plurality of elements of the traversal stack.

9 . The method of claim 8 wherein the plurality of elements are identified as a top-most elements of the traversal stack.

10 . The method of claim 7 wherein the plurality of elements are identified by anticipating when the plurality of elements are to be accessed by the ray tracing acceleration hardware.

11 . The method of claim 7 wherein the cache level identified by the prefetch operation comprises one cache level in a hierarchy of cache levels.

12 . The method of claim 11 wherein the cache level identified by the prefetch operation comprises one of an L2 cache, an L1 cache, and an L0 cache.

13 . The method of claim 7 further comprising:
marking one or more entries of the traversal stack to indicate that associated BVH node data has been prefetched.

14 . A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform:
managing, by ray tracing acceleration hardware, active ray tracing stack allocations within a traversal stack; and performing, by stack management hardware logic, a prefetch operation comprising an indication of bounding volume hierarchy (BVH) node data to be prefetched to perform ray tracing and an indication of a cache level, wherein responsive to performing the prefetch operation, the BVH node data is to be prefetched to the indicated cache level to be accessed by the ray tracing acceleration hardware to perform the ray tracing, wherein a plurality of elements are identified as elements below one or more top-most elements of the traversal stack.

15 . The non-transitory machine-readable medium of claim 14 wherein the prefetch operation is to identify a plurality of elements of the traversal stack.

16 . The non-transitory machine-readable medium of claim 15 wherein the plurality of elements are identified as a top-most elements of the traversal stack.

17 . The non-transitory machine-readable medium of claim 14 wherein the plurality of elements are identified by anticipating when the plurality of elements are to be accessed by the ray tracing acceleration hardware.

18 . The non-transitory machine-readable medium of claim 14 wherein the cache level identified by the prefetch operation comprises one cache level in a hierarchy of cache levels.

19 . The non-transitory machine-readable medium of claim 18 wherein the cache level identified by the prefetch operation comprises one of an L2 cache, an L1 cache, and an L0 cache.

20 . The non-transitory machine-readable medium of claim 14 wherein the program code is to cause the machine to perform:
marking one or more entries of the traversal stack to indicate that associated BVH node data has been prefetched.

Assignees

• Intel Corp

Inventors

• Woop Sven
• Benthin Carsten
• Surti Prasoonkumar
• Barczak Joshua
• Appu Abhishek R
• Majewski Pawel

Classifications

• G06T15/10

  Geometric effects · CPC title

• G06F12/0862

  with prefetch · CPC title

• G06T15/06 Primary

  Ray-tracing · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title