Multi-layered framework for security of integrated circuits

Patent metadata

Field	Value
Publication number	US-12561409-B2
Application number	US-202318327342-A
Country	US
Kind code	B2
Filing date	Jun 1, 2023
Priority date	Jun 2, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

Various embodiments of the present disclosure provide a multi-layered framework for security of integrated circuits. In one example, an embodiment provides for removing one or more routing tables in a Register Transfer Level (RTL) source code that models a design for an SoC via a hardware description language, comprising replacing the one or more routing tables in the RTL source code with respective programmable memory, transforming a state space of one or more embedded state machines in the RTL source code, transforming one or more portions of combinational logic in the RTL source code, and/or removing one or more portions of security-critical logic in the RTL source code, comprising replacing the one or more portions of security-critical logic in the RTL source code with respective lookup tables.

First claim

The invention claimed is:

1 . A method for providing a multi-layered framework for security of integrated circuits, comprising:
providing an attack-resistant obfuscated SoC based on a transformed RTL source code by:
removing one or more routing tables in a Register Transfer Level (RTL) source code that models a design for an SoC via a hardware description language, comprising replacing the one or more routing tables in the RTL source code with respective programmable memory;
transforming a state space of one or more embedded state machines in the RTL source code;
transforming one or more portions of combinational logic in the RTL source code; and
identifying a security-critical logic portion in the RTL source code that corresponds to a control path, a data path, or an interface logic for the SoC; and
replacing the security-critical logic portion in the RTL source code with a lookup table (LUT) associated with LUT-based logic obfuscation to obfuscate the security-critical logic portion via the transformed RTL source code.

2 . The method of claim 1 , wherein the providing the attack-resistant obfuscated SoC comprises performing a multi-layered obfuscation technique by combining multiple countermeasures to transform the RTL source code.

3 . The method of claim 2 , wherein the providing the attack-resistant obfuscated SoC comprises improving security of respective countermeasures of a transformation process for the RTL source code by performing the multi-layered obfuscation technique.

4 . The method of claim 1 , wherein the transforming the state space comprises transforming a portion of the RTL source code that corresponds to the control path, the data path, or the interface logic.

5 . The method of claim 1 , further comprising:
transforming at least one of the control path, the data path, or interface logic associated with the RTL source code based on an algebraic transformation.

6 . The method of claim 1 , wherein the LUT comprises programmable logic for the control path, the data path, or the interface logic.

7 . The method of claim 1 , wherein the providing the attack-resistant obfuscated SoC comprises utilizing unused resources in configurable logic blocks of the RTL source code to minimize design overhead for the transformed RTL source code.

8 . The method of claim 1 , wherein the providing the attack-resistant obfuscated SoC comprises utilizing unused resources in configurable logic blocks of the RTL source code for implementing a Boolean Algebraic Transformation of the RTL source code.

9 . The method of claim 1 , wherein the providing the attack-resistant obfuscated SoC comprises utilizing unused resources in configurable logic blocks of the RTL source code for implementing a State Space Transformation of the RTL source code.

10 . An apparatus comprising at least one processor and at least one memory including program code, the at least one memory and the program code configured to, with the at least one processor, cause the apparatus to at least:
remove one or more routing tables in a Register Transfer Level (RTL) source code that models a design for an SoC via a hardware description language, comprising replacing the one or more routing tables in the RTL source code with respective programmable memory; transform a state space of one or more embedded state machines in the RTL source code; transform one or more portions of combinational logic in the RTL source code; and identify a security-critical logic portion in the RTL source code that corresponds to a control path, a data path, or an interface logic for the SoC; and replace the security-critical logic portion in the RTL source code with a lookup table (LUT) associated with LUT-based logic obfuscation to obfuscate the security-critical logic portion via the transformed RTL source code.

11 . The apparatus of claim 10 , wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least:
perform a multi-layered obfuscation technique by combining multiple countermeasures to transform the RTL source code.

12 . The apparatus of claim 11 , wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least:
improve security of respective countermeasures of a transformation process for the RTL source code by performing the multi-layered obfuscation technique.

13 . The apparatus of claim 10 , wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least:
transform a portion of the RTL source code that corresponds to the control path, the data path, or the interface logic.

14 . The apparatus of claim 10 , wherein the at least one memory and the program code are configured to, with the at least one processor, further cause the apparatus to at least:
transform at least one of the control path, the data path, or interface logic associated with the RTL source code based on an algebraic transformation.

15 . The apparatus of claim 10 , wherein the LUT comprises programmable logic for the control path, the data path, or the interface logic.

16 . A non-transitory computer storage medium comprising instructions, the instructions being configured to cause one or more processors to at least perform operations configured to:
remove one or more routing tables in a Register Transfer Level (RTL) source code that models a design for an SoC via a hardware description language, comprising replacing the one or more routing tables in the RTL source code with respective programmable memory; transform a state space of one or more embedded state machines in the RTL source code; transform one or more portions of combinational logic in the RTL source code; and identify a security-critical logic portion in the RTL source code that corresponds to a control path, a data path, or an interface logic for the SoC; and replace the security-critical logic portion in the RTL source code with a lookup table (LUT) associated with LUT-based logic obfuscation to obfuscate the security-critical logic portion via the transformed RTL source code.

17 . The non-transitory computer storage medium of claim 16 , wherein the operations are further configured to:
perform a multi-layered obfuscation technique by combining multiple countermeasures to transform the RTL source code.

18 . The non-transitory computer storage medium of claim 16 , wherein the operations are further configured to:
transform a portion of the RTL source code that corresponds to the control path, the data path, or the interface logic.

19 . The non-transitory computer storage medium of claim 16 , wherein the operations are further configured to:
transform at least one of the control path, the data path, or interface logic associated with the RTL source code based on an algebraic transformation.

20 . The non-transitory computer storage medium of claim 16 , wherein the LUT comprises programmable logic for the control path, the data path, or the interface logic.

Assignees

• Univ Florida

Inventors

• Bhunia Swarup
• Dasgupta Aritra
• Dizon Reiner
• Bhattacharyay Aritra
• Almawzan Rasheed

Classifications

• G06F21/577 Primary

  Assessing vulnerabilities and evaluating computer system security · CPC title

• G06F2221/033

  Test or assess software · CPC title

• G06F21/76

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F21/14 Primary

  against software analysis or reverse engineering, e.g. by obfuscation · CPC title