Look-up table-based in-memory computing system

Patent metadata

Field	Value
Publication number	US-12561240-B2
Application number	US-202418769985-A
Country	US
Kind code	B2
Filing date	Jul 11, 2024
Priority date	Jul 19, 2023
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

A method and system are directed to providing a look-up table (LUT)-based computation method targeted toward compute-in-memory (CiM) applications. The method comprises a divide and conquer-based approach to provide a solution to scalability challenges in LUT-based mathematical operations for CiM applications. The divide and conquer approach distributes a complex operation into smaller, less complex operations.

First claim

The invention claimed is:

1 . A method for performing computations, the method comprising:
generating, by a most significant bit multiplexer and a least significant bit multiplexer, one or more most significant bit sub-operations and a least significant bit sub-operation that are associated with a computing operation; retrieving, by the most significant bit multiplexer and the least significant bit multiplexer and based on a first input operand and a second input operand, one or more select results from a plurality of results that are associated with the one or more most significant bit sub-operations and the least significant bit sub-operation from a memory array, wherein the one or more select results comprises one or more most significant bit sub-operation results and a least significant bit sub-operation result; generating, by one or more shift registers, one or more left-shifted most significant bit sub-operation results that are associated with the one or more most significant bit sub-operation results based on a determination that the computing operation comprises a multiplication operation; and generating, by a plurality of adders, a result of the computing operation based on an addition operation of the one or more left-shifted most significant bit sub-operation results and the least significant bit sub-operation result.

2 . The method of claim 1 , wherein generating the one or more most significant bit sub-operations and the least significant bit sub-operation comprises distributing the computing operation into a most significant bit multiplication operation and a least significant bit multiplication operation.

3 . The method of claim 1 , wherein generating the one or more left-shifted most significant bit sub-operation results comprises applying one or more left shift operations on the one or more most significant bit sub-operation results.

4 . The method of claim 1 , wherein the first input operand is associated with one or more weights and the second input operand is associated with input data.

5 . The method of claim 1 , wherein the computing operation is associated with a multi-bit multiplier.

6 . The method of claim 1 , wherein the computing operation comprises a 4-bit×4-bit multiplication operation.

7 . The method of claim 1 , wherein the plurality of results comprises (i) a plurality of most significant bit sub-operation results based on a plurality of first input operand values and a plurality of second input operand values and (ii) a plurality of least significant bit sub-operation results based on the plurality of first input operand values and the plurality of second input operand values.

8 . The method of claim 7 , wherein one or more of the plurality of least significant bit sub-operation results comprise one or more fixed values that are associated with one or more approximated results of performing the least significant bit sub-operation.

9 . The method of claim 1 , wherein the first input operand comprises either a programmable value or a fixed value.

10 . A system for performing computations, the system comprising:
a most significant bit multiplexer that is configured to generate a most significant bit sub-operation result that is associated with a computing operation based on a first input operand and a second input operand; a least significant bit multiplexer that is configured to generate a least significant bit sub-operation result that is associated with the computing operation; one or more shift registers that are configured to generate a left-shifted most significant bit sub-operation result; and a plurality of adders that are configured to generate a computing operation output by adding the left-shifted most significant bit sub-operation result with the least significant bit sub-operation result.

11 . The system of claim 10 , wherein the computing operation comprises a 4-bit×4-bit multiplication operation.

12 . The system of claim 10 , wherein the most significant bit multiplexer or the least significant bit multiplexer comprises a plurality of 6-bit multiplexers that are configured to generate the most significant bit sub-operation result or the least significant bit sub-operation result as a 6-bit value.

13 . The system of claim 10 , wherein the most significant bit multiplexer or the least significant bit multiplexer comprises a 2:1 multiplexer.

14 . The system of claim 10 , wherein the most significant bit sub-operation result comprises a 6-bit most significant bit value and the least significant bit sub-operation result comprises a 6-bit least significant bit value.

15 . The system of claim 14 , wherein the plurality of adders is configured to perform an addition operation with the 6-bit most significant bit value and the 6-bit least significant bit value.

16 . The system of claim 15 , wherein the plurality of adders comprises three half adders and three full adders.

17 . The system of claim 10 , wherein the computing operation comprises a single instruction multiple data operation that is performed with the first input operand comprising a weight of a fixed value.

18 . The system of claim 10 , wherein the least significant bit multiplexer is configured to generate the least significant bit sub-operation result based on a fixed value.

19 . The system of claim 10 further comprising a plurality of memory arrays that are coupled to the most significant bit multiplexer and the least significant bit multiplexer in a data read/write path.

20 . A system comprising
one or more processors and at least one memory storing processor-executable instructions that, when executed by any of the one or more processors, causes the one or more processors to perform operations comprising: generating, using a most significant bit multiplexer and a least significant bit multiplexer, one or more most significant bit sub-operations and a least significant bit sub-operation that are associated with a computing operation; retrieving, using the most significant bit multiplexer and the least significant bit multiplexer and based on a first input operand and a second input operand, one or more select results from a plurality of results that are associated with the one or more most significant bit sub-operations and the least significant bit sub-operation from a memory array, wherein the one or more select results comprises one or more most significant bit sub-operation results and a least significant bit sub-operation result; generating, using one or more shift registers, one or more left-shifted most significant bit sub-operation results that are associated with the one or more most significant bit sub-operation results based on a determination that the computing operation comprises a multiplication operation; and generating, using a plurality of adders, a result of the computing operation based on an addition operation of the one or more left-shifted most significant bit sub-operation results and the least significant bit sub-operation result.

Assignees

• Univ Florida

Inventors

• Chatterjee Baibhab
• Bhunia Swarup
• Dehghanzadeh Peyman

Classifications

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/30014

  with variable precision · CPC title

• H03K19/17728

  Reconfigurable logic blocks, e.g. lookup tables · CPC title

• G06F15/7821

  Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory · CPC title