Chip with built-in verification and method for built-in chip verification

Patent metadata

Field	Value
Publication number	US-12561219-B2
Application number	US-202418412702-A
Country	US
Kind code	B2
Filing date	Jan 15, 2024
Priority date	Oct 13, 2023
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

A chip with built-in verification is shown. The signals of key nodes within the chip are collected as operational information. Verification hardware built into the chip includes a plurality of registers, which are programmed to define a branch-type trigger condition. The branch-type trigger condition is formed by sequence-related events. The verification hardware includes an arithmetic module that generates a debugging prompt in response to the branch-type trigger condition defined in the plurality of registers being satisfied by the operational information.

First claim

What is claimed is:

1 . A chip with built-in verification, comprising:
a plurality of key nodes, providing signals to be collected as operational information; and verification hardware, including a plurality of registers which are programmed to define a branch-type trigger condition, wherein the branch-type trigger condition is formed by sequence-related events, and the verification hardware further includes an arithmetic module that generates a debugging prompt in response to the branch-type trigger condition defined in the plurality of registers being satisfied by the operational information; wherein:
the plurality of registers define a plurality of branch event groups, and a plurality of branch events for each branch event group;
the plurality of registers further plan actions in response to when a branch event has been matched, to decide whether to jump to another branch event group or not, or whether to generate the debugging prompt; and
the arithmetic module starts from an initial branch event group to perform branch event matching on the operational information, and jumps between the branch event groups until the arithmetic module generates the debugging prompt to show that the branch-type trigger condition is satisfied.

2 . The chip as claimed in claim 1 , wherein:
each branch event is defined by a characteristic register and a mask register; the operational information is sampled to generate sampled operational information; and the mask register defines whether each bit of the sampled operational information is considered in the branch event matching or not.

3 . The chip as claimed in claim 2 , wherein:
corresponding to each branch event group, the plurality of registers define reference values for system variables; the actions in response to each matched branch event are defined in an action register corresponding to the matched branch event; each action register is programmed so that, in response to when a corresponding branch event has been matched, it is defined how to change the system variables, and how to judge the system variables based on their reference values defined for a current branch event group, to determine whether to jump out of the current branch event group; and each action register further defines that in response to when it has been determined to jump out of the current branch event group, to jump to another branch event group or to generate the debugging prompt.

4 . The chip as claimed in claim 3 , wherein:
the system variables are monitored with counters and timers.

5 . The chip as claimed in claim 1 , wherein:
the verification hardware further includes a sampling module; the sampling module samples the operational information based on a quadruple-frequency clock, to generate sampled operational information; and the sampled operational information is processed by the arithmetic module according to one-times frequency clock, to check the branch-type trigger condition.

6 . The chip as claimed in claim 5 , wherein:
the sampling module operates according to rising edges and falling edges of a double frequency clock.

7 . The chip as claimed in claim 6 , wherein:
the sampling module includes a plurality of D flip-flops which are connected in series, and the D flip-flops connected in series operate according to the quadruple-frequency clock, wherein a first stage of the D flip-flops connected in series receives the operational information; and the sampling module further includes a plurality of parallel sampling D flip-flops, the parallel sampling D flip-flops operate according to the one-times frequency clock to sample output signals from final stages of the D flip-flops connected in series, and the parallel sampling D flip-flops output different batches of the sampled operational information in parallel.

8 . The chip as claimed in claim 7 , wherein:
the D flip-flops connected in series are numbered from 0 to 6 from their input stage to their end stage; the parallel sampling D flip-flops are numbered from 0 to 3; the parallel sampling D flip-flop of number 0 samples an output signal from the D flip-flop of number 6 based on the one-times frequency clock, and outputs information with number 0; the parallel sampling D flip-flop of number 1 samples an output signal from the D flip-flop of number 5 based on the one-times frequency clock, and outputs information with number 1; the parallel sampling D flip-flop of number 2 samples an output signal from the D flip-flop of number 4 based on the one-times frequency clock, and outputs information with number 2; and the parallel sampling D flip-flop of number 3 samples an output signal from the D flip-flop of number 3 based on the one-times frequency clock, and outputs information with number 3.

9 . The chip as claimed in claim 7 , without any logic components between adjacent D flip-flops which are connected in series.

10 . The chip as claimed in claim 7 , wherein the arithmetic module comprises:
a branch event matching module, comparing each batch of the sampled operational information with all branch events of the different branch event groups to obtain a matching record for each batch of the sampled operational information, wherein different record bits of one matching record correspond to the different branch events; a first-in-first-out buffer, storing outputs of the branch event matching module, to buffer matching records in chronological order; and a branch analysis module, retrieving the matching records from the first-in-first-out buffer to identify a valid matching bit of each matching record, wherein, based on an action register corresponding to a branch event marked by the valid matching bit, the branch analysis module decides whether to jump to another branch event group or not, or to generate the debugging prompt.

11 . The chip as claimed in claim 10 , wherein the branch analysis module comprises at least one branch analysis sub-circuit, for separately processing the matching records taken from the first-in-first-out buffer, and each branch analysis sub-circuit comprises:
a plurality of multiplexers, each corresponding to a branch event number to receive record bits of branch events with the branch event number in the different branch event groups, and operating according to a group selection signal, wherein outputs of the multiplexers are transformed into a valid symbol that indicates the valid matching bit; a plurality of action modules, each corresponding to a branch event number to generate an action prediction based on an action register of a branch event of the branch event number within a target branch event group selected by the group selection signal, to predict whether to jump to another branch event group or not, or whether to generate the debugging prompt; and an action multiplexer, receiving the group selection signal as well as every action prediction provided by the action modules, to output an action indication according to the valid symbol, wherein the action indication indicates whether to jump to another branch event group or not, or whether to generate the debugging prompt.

12 . The chip as claimed in claim 11 , wherein each action module corresponds to a target branch event number, and comprises:
a plurality of action sub-modules, receiving the record bits corresponding to the target branch event number with respect to the different branch event groups, wherein each action sub-module performs action prediction according to a corresponding action register; a prediction multiplexer, receiving action predictions from the action sub-modules and operating according to the group selection signal, to output one of

Assignees

• Shanghai Zhaoxin Semiconductor Co Ltd

Inventors

• Yang Qunyi
• Yang Fan
• Wang Xu
• Cheng Zhongxiang

Classifications

• G06F11/2236 Primary

  to test CPU or processors · CPC title

• G06F11/27 Primary

  Built-in tests · CPC title

• G06F5/065

  Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title