Application programming interface to cause operator to be used by compiler

Patent metadata

Field	Value
Publication number	US-12561184-B2
Application number	US-202217585293-A
Country	US
Kind code	B2
Filing date	Jan 26, 2022
Priority date	Jan 26, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

Apparatuses, systems, and techniques to add operators to a compiler. In at least one embodiment, one or more operators are added to a compiler using one or more application programming interfaces (APIs).

First claim

What is claimed is:

1 . A non-transitory machine-readable medium having stored thereon instructions of one or more application programming interfaces (APIs) which, if performed by one or more processors, cause the one or more processors to:
receive one or more calls to the one or more APIs; and in response to receipt of the one or more calls, cause a compiler to generate object code based, at least in part, on one or more symbols within source code to be compiled by the compiler, a parameter of the one or more APIs specifying one or more portions of code comprising code corresponding to the one or more symbols, and information to generate a size of memory to be allocated to perform the corresponding code.

2 . The non-transitory machine-readable medium of claim 1 , wherein the one or more symbols correspond to one or more operators, previously unregistered with the compiler, to perform one or more operations by code generated by the compiler.

3 . The non-transitory machine-readable medium of claim 2 , wherein the one or more operators correspond to a sequence of one or more operators of the compiler to be performed by code generated by the compiler.

4 . The non-transitory machine-readable medium of claim 2 , wherein the instructions, if performed by the one or more processors, cause the one or more processors to, in response to the receipt of the one or more calls, further load one or more libraries comprising one or more instructions to be used by the compiler in response to the one or more operators.

5 . The non-transitory machine-readable medium of claim 2 , wherein the compiler is to generate one or more intermediate representation (IR) data in response to using the one or more operators.

6 . The non-transitory machine-readable medium of claim 2 , wherein the instructions, if performed by the one or more processors, cause the one or more processors to, in response to the receipt of the one or more calls, further load one or more data files comprising one or more instructions to perform the one or more operators to be used by one or more software programs output by the compiler.

7 . The non-transitory machine-readable medium of claim 1 , wherein the instructions, if performed by the one or more processors, cause the one or more processors to, in response to the receipt of the one or more calls, further create one or more namespaces to correspond to the one or more symbols.

8 . The non-transitory machine-readable medium of claim 1 , wherein the instructions, if performed by the one or more processors, cause the one or more processors to, in response to the receipt of the one or more calls, further generate one or more pattern matching rules to be used during compilation to identify the one or more symbols.

9 . A system comprising:
one or more processors; and memory storing thereon instructions of one or more application programming interfaces (APIs) which, if performed by the one or more processors, cause the one or more processors to: receive one or more calls to the one or more APIs; and in response to receipt of the one or more calls, cause a compiler to generate object code based, at least in part, on one or more symbols within source code to be compiled by the compiler, a parameter of the one or more APIs specifying one or more portions of code comprising code corresponding to the one or more symbols, and information to generate a size of memory to be allocated to perform the corresponding code.

10 . The system of claim 9 , wherein the compiler is to generate one or more programs using one or more instructions indicated to the one or more calls APIs to perform one or more operators corresponding to the one or more symbols.

11 . The system of claim 9 , wherein the one or more symbols are to cause the compiler using the source code to generate executable code to perform one or more computational operations previously unsupported by the compiler.

12 . The system of claim 9 , wherein the instructions, if performed by the one or more processors, cause the one or more processors to, in response to the receipt of the one more calls, further generate one or more operators corresponding to the one or more symbols based, at least in part, on one or more other operations usable by the compiler.

13 . The system of claim 9 , wherein the instructions, if performed by the one or more processors, cause the one or more processors to, in response to the receipt of the one or more calls, further perform instructions of one or more other APIs in response to one or more operators being used by the compiler, the one or more operators corresponding to the one or more symbols.

14 . The system of claim 9 , wherein the compiler is to generate one or more patterns usable to identify one or more operators corresponding to the one or more symbols in response to the receipt of the one or more calls.

15 . The system of claim 9 , wherein the instructions, if performed by the one or more processors, cause the one or more processors to, in response to the receipt of the one or more calls, further cause the compiler to generate one or more data structures usable to represent one or more operators corresponding to the one or more symbols and generate one or more output files based, at least in part, on the one or more operators.

16 . One or more processors, comprising: circuitry to:
receive one or more calls to one or more application programming interfaces (APIs); and in response to receipt of the one or more calls, cause a compiler to generate object code based, at least in part, on one or more symbols within source code to be compiled by the compiler, a parameter of the one or more APIs specifying one or more portions of code comprising code corresponding to the one or more symbols, and information to generate a size of memory to be allocated to perform the corresponding code.

17 . The one or more processors of claim 16 , wherein the circuitry is to, in response to the receipt of the one or more calls, further cause the compiler to generate one or more outputs to perform one or more operators corresponding to the one or more symbols based, at least in part, on one or more source files input to the compiler invoking the one or more APIs.

18 . The one or more processors of claim 17 , wherein the circuitry is to, in response to the receipt of the one or more calls, further load one or more library files comprising one or more instructions to be usable to generate, by the compiler, one or more output files to perform the one or more operators.

19 . The one or more processors of claim 17 , wherein the compiler is to generate one or more rules to identify the one or more operators in one or more source code files to be compiled in response to the one or more APIs.

20 . The one or more processors of claim 17 , wherein the compiler is to generate one or more data structures usable to generate code representing the one or more operators in response to the one or more APIs.

21 . The one or more processors of claim 17 , wherein the one or more operators are to cause the compiler to generate one or more output files to perform one or more other operators used by the compiler.

22 . A method comprising:
receiving one or more calls to one or more application programming interfaces (APIs); and in response to receipt of the one or more calls, causing a compiler to generate object code based, at least in part, on one or more symbols within source code to be compiled by the compiler, a

Assignees

• Nvidia Corp

Inventors

• Gaburov Evghenii
• Fan Bin
• Collins Alexander James
• Grover Vinod

Classifications

• G06F8/44

  Encoding · CPC title

• G06F9/505

  considering the load · CPC title

• G06F8/41 Primary

  Compilation · CPC title

• G06F9/541 Primary

  via adapters, e.g. between incompatible applications · CPC title

• G06F9/5077 Primary

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title