Accelerated data processing in solid state drives (SSDs) with host processors and storage processing engines (SPEs)

Patent metadata

Field	Value
Publication number	US-12561057-B2
Application number	US-202318370817-A
Country	US
Kind code	B2
Filing date	Sep 20, 2023
Priority date	Dec 5, 2018
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

A system includes a plurality of storage processing accelerators (SPAs), at least one SPA of the plurality of SPAs including a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs including n SPEs (n is a natural number greater than zero), where 1st to (n−1) SPEs of the n SPEs are configured to provide an output of the SPE to a next SPE of the n SPEs in a pipeline to be used as an input of the next SPE; and an acceleration platform manager (APM) connected to the plurality of the SPAs and the plurality of SPEs, and configured to control data processing in the plurality of SPAs and the plurality of SPEs.

First claim

What is claimed is:

1 . A system comprising:
a first processor connected to a second processor; and a third processor connected to at least one of the first processor or the second processor, the third processor comprising a management module, wherein the first processor provides an output to the second processor, wherein the second processor performs one or more operations on the output of the first processor, wherein the third processor controls data processing in at least one of the first processor or the second processor, and wherein the first processor and the second processor comprise one or more storage processing accelerators (SPAs) and the first processor and the second processor comprise two or more storage processing engines (SPEs), wherein the one or more SPAs run in parallel on different slices of data received at the management module.

2 . The system of claim 1 , wherein at least one of the first processor or the second processor performs one or more operations associated with an acceleration process.

3 . The system of claim 1 , wherein the third processor performs one or more operations associated with a management process.

4 . The system of claim 1 , wherein the third processor comprises a management module, wherein the management module:
programs one or more arguments received from a service manager in the first processor; creates and programs one or more data movement descriptors; and sends a result to the service manager.

5 . The system of claim 4 , further comprising a host processor, wherein the host processor:
gathers first information comprising one or more of source of data for processing an application function call, type of processing of the application function call, arguments for the application function call, and destination of the result based on processed data; and receives the first information, wherein based on receiving the first information the system: selects a processor comprising the management module for application function processing; initiates data transfer engines to load appropriate data into one or more buffers of the processor; and sends a signal and the first information to the processor.

6 . The system of claim 4 , wherein the first processor and the second processor comprise at least one of an input memory or an output memory, wherein the system further comprises a multiplexer that multiplexes outputs of the first processor and the second processor into the output memory.

7 . The system of claim 4 , wherein an input data buffer (IDB) is shared between two processors.

8 . The system of claim 4 , wherein the first processor comprises an input data buffer (IDB), wherein the first processor writes the output of the first processor into an IDB of the second processor,
wherein instructions running on the first processor generates batch indications to the second processor.

9 . The system of claim 8 , further comprising one or more solid state drives (SSDs) connected to a processor comprising the management module, wherein the management module obtains data from the one or more SSDs to be processed by the first processor and the second processor.

10 . The system of claim 4 , wherein the management module accesses one or more of instruction memory and data memory via the first processor.

11 . The system of claim 10 , wherein the first processor comprises a first bus for the instruction memory and a second bus for the data memory.

12 . The system of claim 11 , wherein the data memory comprises at least one of scratch pad, input data buffer (IDB), output data buffer (ODB), argument memory, or miscellaneous memory, wherein one or more features of the first processor and the second processor are based on the miscellaneous memory and accessed by instructions running on the first processor as pointers.

13 . A system comprising:
a first processor connected to a second processor; and a third processor connected to at least one of the first processor or the second processor, the third processor comprising a management module, wherein the first processor provides an output to the second processor, and wherein the third processor controls data processing in at least one of the first processor or the second processor, and wherein the first processor and the second processor comprise one or more storage processing accelerators (SPAs) and the first processor and the second processor comprise two or more storage processing engines (SPEs), wherein the one or more SPAs run in parallel on different slices of data received at the management module.

14 . The system of claim 13 ,
wherein the second processor performs one or more operations on the output of the first processor, and wherein the management module:
allocates one of the first processor or the second processor;
provides instructions into a first SPE of the two or more SPEs;
obtains data based on first information received from a service manager;
programs one or more arguments received from the service manager in the first SPE of the two or more SPEs;
creates and program one or more data movement descriptors; and
sends, a result to the service manager.

15 . The system of claim 14 , wherein the first processor and the second processor comprise at least one of an input memory or an output memory, wherein the first SPE comprises an input data buffer (IDB), and wherein the first SPE writes an output of the first SPE into an IDB of a second SPE.

16 . The system of claim 15 , further comprising one or more solid state drives (SSDs) connected to the third processor comprising the management module, wherein the management module obtains data from the one or more SSDs to be processed by the two or more SPEs.

17 . The system of claim 13 , wherein at least one of the first processor or the second processor performs one or more operations associated with an acceleration process, and
wherein the third processor performs one or more operations associated with a management process.

18 . A device comprising:
a cluster comprising a first processor connected to a second processor; a third processor connected to the cluster, the first processor, and the second processor; and one or more solid state drives (SSDs) connected to the third processor comprising a management module, wherein the first processor provides an output to the second processor, wherein the third processor controls data processing in at least one of the cluster, the first processor, or the second processor, and
wherein the first processor and the second processor comprise two or more storage processing engines (SPEs), wherein the two or more SPEs are arranged in clusters, wherein the cluster is a storage processing accelerator (SPA), and wherein the management module extracts data from the one or more SSDs to be processed by the two or more SPEs.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kachare Ramdas P
• Balakrishnan Vijay
• Fischer Stephen G
• WORLEY Fred
• Shayesteh Anahita
• Guz Zvi

Classifications

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F9/541

  via adapters, e.g. between incompatible applications · CPC title

• G06F9/544

  Buffers; Shared memory; Pipes · CPC title

• G06F9/38

  Concurrent instruction execution, e.g. pipeline or look ahead · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title