Dual-side folded source driver outputs of a display panel having a narrow border

Patent metadata

Field	Value
Publication number	US-12560844-B2
Application number	US-202217974407-A
Country	US
Kind code	B2
Filing date	Oct 26, 2022
Priority date	May 28, 2021
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

An electronic device has a display substrate including a display area, a driver area, and a fan-out area. The fan-out area has interconnects that provide electrical accesses to display elements on the display area. A driver chip is disposed on the driver area and includes a first edge adjacent to the display area, two side edges connected to the first edge, and a plurality of pad groups. Each pad group includes a row of electronic pads that are electrically coupled to a subset of display elements via a subset of interconnects routed on the fan-out area. The pad groups include a first pad group and a second pad group disposed immediately adjacent to the first pad group. A first subset of interconnects cross one of the two side edges, and extend above a gap between rows of the first and second pad groups to reach the first pad group.

First claim

What is claimed is:

1 . An electronic device, comprising:
a display substrate including a display area, a driver area, and a fan-out area, the fan-out area having a plurality of interconnects configured to provide electrical accesses to a plurality of display elements of the display area; and a driver chip disposed on the driver area of the display substrate, the driver chip further including:
a first edge adjacent to the display area;
two side edges connected to the first edge;
a third edge that opposes the first edge; and
a plurality of pad groups, each pad group including a respective row of electronic pads that are electrically coupled to a respective subset of display elements via a respective subset of interconnects routed on the fan-out area;
wherein the plurality of pad groups include a first pad group and a second pad group disposed adjacent to, and extending in parallel with, the first pad group; wherein a gap is formed between respective rows of electronic pads of the first and second pad groups; wherein a first subset of interconnects cross one of the two side edges, and extend above the gap to reach the first pad group; and wherein the display substrate further includes a fan-in area disposed adjacent to the third edge, and flexible printed circuit (FPC) is disposed on the fan-in area to provide one or more input signals to the driver chip.

2 . The electronic device of claim 1 , wherein for each pad group, the respective row of electronic pads is arranged substantially in parallel with the first edge and has a respective distinct distance from the first edge.

3 . The electronic device of claim 1 , wherein the second pad group is closer to the first edge of the driver chip and the display area than the first pad group.

4 . The electronic device of claim 3 , wherein a second subset of interconnects that are electrically coupled to the second pad group cross the first edge of the driver chip and does not extend above the gap between the respective row of electronic pads of the first and second pad groups.

5 . The electronic device of claim 1 , wherein the first pad group is closer to the first edge of the driver chip and the display area than the second pad group.

6 . The electronic device of claim 5 , wherein the third edge is connected to the two side edges, and a second subset of interconnects that are electrically coupled to the second pad group cross the third edge of the driver chip and does not extend above the gap.

7 . The electronic device of claim 6 , wherein:
the plurality of pad groups include an input/output pad group located immediately adjacent to the third edge; and the second pad group and the input/output pad group are aligned with a pad line that is parallel with the first and third edges.

8 . The electronic device of claim 1 , wherein the plurality of pad groups includes a third pad group immediately adjacent to the first pad group, and no interconnect is routed to extend above a second gap formed between the respective row of electronic pads of the first and third pad groups.

9 . The electronic device of claim 1 , wherein a second subset of interconnects that are electrically coupled to the second pad group cross the one of the two side edges, and extend above the gap.

10 . The electronic device of claim 1 , wherein a second subset of interconnects that are electrically coupled to the second pad group cross the one of the two side edges, and extend above a second gap formed between the respective rows of electronic pads of the second pad group and a third pad group, the third pad group immediately adjacent to the second pad group.

11 . The electronic device of claim 1 , wherein each of the first pad group and the second pad group includes a predefined number of pads, and the first and second pad groups are aligned at two ends of the respective rows of electronic pads of the first and second pad groups.

12 . The electronic device of claim 1 , wherein the gap is formed between a subset of the first pad group and a subset of the second pad group, and each of the subsets of the first and second pad groups includes at least two electronic pads.

13 . The electronic device of claim 1 , wherein the driver chip further comprises:
a plurality of source drivers configured to drive the plurality of display elements, wherein for each pad group, the respective row of electronic pads are electrically coupled to a respective subset of source drivers, allowing the respective subset of source drivers to be electrically coupled to the respective subset of display elements via the respective subset of interconnects routed on the fan-out area.

14 . The electronic device of claim 1 , wherein the plurality of interconnects are formed on a single layer of conductive material, cannot cross each other, and are spatially ordered on the display substrate, and the fan-out area at least partially surrounding the driver area.

15 . The electronic device of claim 1 , wherein the driver chip is flip-chip assembled to the display substrate, thereby facilitating the respective row of electronic pads of each pad group to physically contact the respective subset of interconnects; and
wherein the electronic device is one of a laptop display, a tablet computer display, and a mobile phone display, and the driver chip includes at least a source driver configured to drive the plurality of display elements and a timing controller configured to control driving of the plurality of display elements in a synchronous manner.

16 . The electronic device of claim 1 , the driver chip including a first driver chip, the electronic device further comprising one or more of:
a second driver chip that is identical to the first driver chip and disposed in the driver area, wherein the first edges of the first and second driver chips are aligned and arranged in parallel with a display edge of the display area; and one or more third driver chips that are identical to the first driver chip and disposed in the driver area, wherein the first edges of the first, second and third driver chips are aligned and arranged in parallel with the display edge of the display area, and the first, second, and third driver chips are equally spaced.

17 . An electronic device, comprising:
a display substrate including a display area, a driver area, and a fan-out area, the fan-out area having a plurality of interconnects configured to provide electrical accesses to a plurality of display elements of the display area; and a driver chip disposed on the driver area of the display substrate, the driver chip further including:
a first edge adjacent to the display area;
two side edges connected to the first edge; and
a plurality of pad groups, each pad group including a respective row of electronic pads that are electrically coupled to a respective subset of display elements via a respective subset of interconnects routed on the fan-out area;
wherein the plurality of pad groups include a first pad group and a second pad group disposed immediately adjacent to the first pad group, and a first subset of interconnects cross one of the two side edges, and extend above a gap between respective rows of electronic pads of the first and second pad groups to reach the first pad group; and wherein for each pad group:
the respective row of electronic pads includes a respective first row of electronic pads;
the respective pad group includes a respective second row of electronic pads; and
the respective second row of electronic pads are arranged substantially in parallel with the first ed

Assignees

• Parade Tech Ltd

Inventors

• Yin You Ben
• Yu Quan

Classifications

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W90/00

  Package configurations · CPC title