Wire bonding method and apparatus for electromagnetic interference shielding

Patent metadata

Field	Value
Publication number	US-12557659-B2
Application number	US-202418788822-A
Country	US
Kind code	B2
Filing date	Jul 30, 2024
Priority date	Jul 29, 2016
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

First claim

What is claimed is:

1 . A packaged microelectronic device, comprising:
a first device disposed on a platform; a second device disposed on the platform; a third device disposed on the platform; a first interference shield comprising a first plurality of wire bond wires, wherein:
at least a portion of the first interference shield is disposed between the first device and the second device; and
at least a portion of the first interference shield is disposed between the third device and the second device;
a second interference shield comprising a second plurality of wire bond wires, wherein:
at least a portion of the second interference shield is disposed between the first device and the second device; and
at least a portion of the second interference shield is disposed between the third device and the second device;
a first spacing between a first adjacent pair of wire bond wires in the first interference shield; and a second spacing between a second adjacent pair of wire bond wires in the second interference shield, wherein the second spacing is different than the first spacing.

2 . The packaged microelectronic device of claim 1 , wherein the platform is a circuit board.

3 . The packaged microelectronic device of claim 1 , wherein the platform is a substrate.

4 . The packaged microelectronic device of claim 1 , wherein the platform is a redistribution layer.

5 . The packaged microelectronic device of claim 1 , wherein the platform is a silicon substrate.

6 . The packaged microelectronic device of claim 1 , further comprising a third interference shield comprising a third plurality of wire bond wires, wherein at least a portion of the third interference shield is disposed between the third device and the first device.

7 . The packaged microelectronic device of claim 1 , wherein:
the first spacing is about 1/10th or less than a first wavelength of electromagnetic radiation of a first frequency; and the second spacing is about 1/10th or less than a second wavelength of electromagnetic radiation of a second frequency.

8 . The packaged microelectronic device of claim 1 , further comprising a fourth device disposed on the platform, wherein at least a portion of the first interference shield is disposed between the first device and the fourth device.

9 . The packaged microelectronic device of claim 8 , wherein at least a portion of the first interference shield is disposed between the fourth device and the third device.

10 . The packaged microelectronic device of claim 8 , wherein at least a portion of the second interference shield is disposed between the fourth device and the second device.

11 . The packaged microelectronic device of claim 1 , further comprising a fourth device disposed on the platform, wherein at least a portion of the second interference shield is disposed between the second device and the fourth device.

12 . The packaged microelectronic device of claim 11 , wherein at least a portion of the first interference shield is disposed between the fourth device and the first device.

13 . A packaged microelectronic device, comprising:
a first device disposed on a platform; a second device disposed on the platform; a third device disposed on the platform; a first interference shield comprising a first plurality of wire bond wires, wherein:
the first interference shield intersects a shortest path between the first device and the second device, and
the first interference shield intersects a shortest path between the third device and the second device;
a second interference shield comprising a second plurality of wire bond wires, wherein:
the second interference shield intersects the shortest path between the first device and the second device, and
the second interference shield intersects the shortest path between the third device and the second device;
a first spacing between a first adjacent pair of wire bond wires in the first interference shield; and a second spacing between a second adjacent pair of wire bond wires in the second interference shield, wherein the second spacing is larger than the first spacing.

14 . The packaged microelectronic device of claim 13 , wherein the platform is a circuit board.

15 . The packaged microelectronic device of claim 13 , wherein the platform is a substrate.

16 . The packaged microelectronic device of claim 13 , wherein the platform is a redistribution layer.

17 . The packaged microelectronic device of claim 13 , wherein the platform is a silicon substrate.

18 . The packaged microelectronic device of claim 13 , further comprising a third interference shield comprising a third plurality of wire bond wires, wherein at least a portion of the third interference shield is disposed between the third device and the first device.

19 . The packaged microelectronic device of claim 13 , wherein:
the first spacing is about 1/10th or less than a first wavelength of electromagnetic radiation of a first frequency; and the second spacing is about 1/10th or less than a second wavelength of electromagnetic radiation of a second frequency.

20 . A packaged microelectronic device, comprising:
a first device disposed on a platform; a second device disposed on the platform; a third device disposed on the platform; a first interference shield comprising a first plurality of wire bond wires, wherein:
the first device and the third device are on a first side of the first interference shield; and
the second device is on a second side of the first interference shield;
a second interference shield comprising a second plurality of wire bond wires, wherein:
the first device and the third device are on a first side of the second interference shield; and
the second device is on a second side of the second interference shield;
a first spacing between a first adjacent pair of wire bond wires in the first interference shield; and a second spacing between a second adjacent pair of wire bond wires in the second interference shield, wherein the second spacing is different than the first spacing.

Assignees

• Adeia Semiconductor Tech Llc

Inventors

• Huang Shaowu
• Delacruz Javier A

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W74/017

  Auxiliary layers for moulds, e.g. release layers or layers preventing residue · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W42/273

  the arrangements being between laterally adjacent chips, e.g. walls between chips · CPC title