Display panel and display device

Patent metadata

Field	Value
Publication number	US-12557495-B2
Application number	US-202117925503-A
Country	US
Kind code	B2
Filing date	Dec 27, 2021
Priority date	Dec 27, 2021
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A display panel includes a base substrate including a display area and a peripheral area surrounding the display area, the display area comprises a first display area and a second display area, the first display area at least partially surrounds the second display area; a plurality of first/second pixel circuits located in the first/second display area; a plurality of first initialization signal lines, located at least in the first display area and extending in a first direction, being electrically connected to the first pixel circuit and configured to transmit a first initial voltage signal to the first pixel circuit; a plurality of second initialization signal lines, located at least in the first display area and the second display area, and electrically connected to the second pixel circuit, configured to transmit a second initial voltage signal to the second pixel circuit; the first and second initial voltage signals being different.

First claim

What is claimed is:

1 . A display panel, comprising a base substrate, wherein the base substrate comprises a display area and a peripheral area at least partially surrounding the display area, the display area comprises a first display area and a second display area, the first display area at least partially surrounds the second display area;
a plurality of first pixel circuits located in the first display area; a plurality of second pixel circuits located in the second display area; a plurality of first initialization signal lines, located at least in the first display area and extending in a first direction, the first initialization signal lines being electrically connected to the first pixel circuit and configured to transmit a first initial voltage signal to the first pixel circuit; a plurality of second initialization signal lines, located at least in the first display area and the second display area, and electrically connected to the second pixel circuit, configured to transmit a second initial voltage signal to the second pixel circuit; the first initial voltage signal and the second initial voltage signal being different; wherein a voltage of the first initial voltage signal is higher than a voltage of the second initial voltage signal.

2 . The display panel according to claim 1 , wherein the second initialization signal line comprises a first part located in the first display area and a second part located in the second display area, the second part is connected to the second pixel circuit.

3 . The display panel according to claim 1 , wherein the display panel further comprises a third initialization signal line; the third initialization signal line at least partially surrounds the second pixel circuit, and the plurality of first initialization signal lines is connected to the third initialization signal line.

4 . The display panel according to claim 3 , wherein the third initialization signal line and a first part of the second initialization signal line located in the first display area are arranged at a same layer, and the plurality of first initialization signal lines and a second part of the second initialization signal line located in the second display area are arranged at a same layer, the first part and the second part are electrically connected to each other and arranged at different layers.

5 . The display panel according to claim 3 , wherein the third initialization signal line is located in the first display area or the second display area, and the third initialization signal line is in a closed ring shape.

6 . The display panel according to claim 1 , wherein the display panel further comprises a first initialization bus and a second initialization bus located in the peripheral area, the plurality of first initialization signal lines is connected to the first initialization bus, and the plurality of second initialization signal lines is connected to the second initialization bus.

7 . The display panel according to claim 6 , wherein the first initialization bus is located on a side of the second initialization bus away from the base substrate.

8 . The display panel according to claim 6 , wherein the first initialization bus comprises a first sub-line and a second sub-line; the first sub-line and the second sub-line are located on both sides of the display area;
the second initialization bus includes a third sub-line and a fourth sub-line, and the third sub-line and the fourth sub-line are located on both sides of the display area.

9 . The display panel according to claim 1 , wherein the plurality of first pixel circuits comprises a plurality of first pixel groups, and the plurality of second pixel circuits comprises a plurality of second pixel groups;
different first pixel groups are connected to different first initialization signal lines in the first display area; different second pixel groups are connected to different second initialization signal lines in the second display area.

10 . The display panel according to claim 9 , wherein a plurality of first pixel circuits located in a same first pixel group is sequentially arranged in a straight line along the first direction; a plurality of second pixel circuits located in a same second pixel group is staggered along a second direction.

11 . The display panel according to claim 1 , wherein, in the first display area, at least part of the plurality of first initialization signal lines and at least part of the plurality of second initialization signal lines are alternately arranged along a second direction; the second direction intersects the first direction.

12 . The display panel according to claim 4 , wherein the plurality of the first pixel circuits and the plurality of the second pixel circuits respectively comprise thin film transistors arranged on the base substrate, the thin film transistor comprises an active layer, a gate electrode and a source/drain electrode that are sequentially arranged in a direction away from the base substrate;
the display panel further includes a light shielding layer arranged between the base substrate and the active layer; wherein, the plurality of first initialization signal lines, the second part and the gate electrode are arranged at a same layer and made of a same material; the third initialization signal line, the first part, and the active layer are arranged at a same layer and made of a same material; or, the third initialization signal line, the first part, and the light shielding layer are arranged at a same layer and made of a same material; or, the third initialization signal line, the first part and the source-drain layer are arranged at a same layer and made of a same material.

13 . The display panel according to claim 12 , wherein the first part and the second part are electrically connected through a first connection layer, and the plurality of first initialization signal lines and the third initialization signal line are electrically connected through a second connection layer;
the first connection layer and the second connection layer are arranged at a same layer and made of a same material.

14 . The display panel according to claim 13 , wherein the first connection layer, the second connection layer and the source/drain electrodes are arranged at a same layer and made of a same material.

15 . The display panel according to claim 12 , wherein the plurality of first initialization signal lines and the plurality of second initialization signal lines are respectively electrically connected to source/drain electrodes of thin film transistors.

16 . The display panel according to claim 1 , wherein the second display area is a light transmitting display area, and a density of the plurality of second pixel circuits in the second display area is less than or equal to a density of the plurality of first pixel circuits in the first display area.

17 . The display panel according to claim 1 , wherein the display area further comprises a plurality of auxiliary signal lines located in the first display area and extending along the first direction;
the plurality of auxiliary signal lines is not connected to any one of the first pixel circuits and any one of the second pixel circuits.

18 . The display panel according to claim 17 , wherein the auxiliary signal line and a part of the second initialization signal line are arranged at a same layer and made of a same material.

19 . A display device, comprising the display panel according to claim 1 .

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Fang Fei
• Liu Ke
• Shi Ling
• Tian Xuewei
• Lu Hui
• Xie Shuai
• Guo Dan

Classifications

• G09G3/32

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title