Method of manufacturing semiconductor structure and semiconductor structure

Patent metadata

Field	Value
Publication number	US-12557262-B2
Application number	US-202318149236-A
Country	US
Kind code	B2
Filing date	Jan 3, 2023
Priority date	Apr 29, 2022
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method of manufacturing the semiconductor structure includes: providing a base, where contact structures arranged at intervals are formed on a surface of the base; forming, on the base, a stacked structure including alternately stacked a support layer and a sacrificial layer, where the stacked structure covers the contact structure; forming an isolation structure in the stacked structure, where the isolation structure runs through the sacrificial layer and part of the support layer along a direction perpendicular to the base, and is connected to the base through part of a remaining support layer, to divide the base into a first region and a second region; and forming a capacitor structure in the second region, where the capacitor structure is correspondingly connected to the contact structure in the second region.

First claim

The invention claimed is:

1 . A method of manufacturing a semiconductor structure, wherein the method of manufacturing the semiconductor structure comprises:
providing a base, wherein spaced contact structures are formed on a surface of the base; forming, on the base, a stacked structure comprising alternately stacked a support layer and a sacrificial layer, wherein the stacked structure covers the contact structure; forming an isolation structure in the stacked structure, wherein the isolation structure runs through the sacrificial layer and part of the support layer along a direction perpendicular to the base, and is connected to the base through part of a remaining support layer, to divide the base into a first region and a second region; and forming a capacitor structure in the second region, wherein the capacitor structure is correspondingly connected to the contact structure in the second region; wherein the forming, on the base, a stacked structure comprising a support layer and a sacrificial layer that are alternately stacked comprises: forming, on the base, a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer, and a third support layer that are stacked, wherein the first support layer, the second support layer, and the third support layer form a support structure; wherein the forming an isolation structure in the stacked structure comprises: etching the third support layer, the second sacrificial layer, the second support layer, and the first sacrificial layer along the direction perpendicular to the base, to form an isolation hole; and filling the isolation hole with an isolation material to form the isolation structure, wherein a bottom surface of the isolation structure is connected to the base through the first support layer, and a top surface of the isolation structure is flush with a top surface of the third support layer; wherein a material of the isolation structure is silicon nitride.

2 . The method of manufacturing the semiconductor structure according to claim 1 , wherein the capacitor structure has an extension portion along a direction toward the first region, and the extension portion extends into the first region and covers a top surface and a sidewall of the isolation structure.

3 . The method of manufacturing the semiconductor structure according to claim 1 , wherein the forming capacitor structures in the second region comprises:
forming spaced capacitor holes in the second region, wherein a bottom of the capacitor hole exposes a top surface of the contact structure; forming a first electrode layer on an inner wall of the capacitor hole, wherein the first electrode layer in the capacitor hole forms a first recess; forming a dielectric layer on an inner wall of the first recess, wherein an end of the dielectric layer toward the isolation structure extends out of the first recess and covers the top surface and a sidewall of the isolation structure; and forming a second electrode structure on an outer surface of the dielectric layer.

4 . The method of manufacturing the semiconductor structure according to claim 3 , wherein the forming a first electrode layer on an inner wall of the capacitor hole comprises:
forming a first initial electrode layer on the inner wall of the capacitor hole, wherein the first initial electrode layer extends out of the capacitor hole and covers a top surface of the stacked structure and the top surface of the isolation structure in the first region, and the first initial electrode layer further covers a top surface of the stacked structure in the second region; removing, in a same etching step, part of the first initial electrode layer between adjacent capacitor holes, and the first initial electrode layer located on the top surface of the stacked structure in the first region; and removing the first initial electrode layer located on the top surface of the isolation structure, wherein the remaining part of the first initial electrode layer forms the first electrode layer.

5 . The method of manufacturing the semiconductor structure according to claim 4 , wherein the removing part of the first initial electrode layer between adjacent capacitor holes, and the first initial electrode layer located on the top surface of the stacked structure in the first region comprises:
forming, on the first initial electrode layer, a first dielectric layer and a dielectric anti-reflective coating layer that are stacked; patterning the dielectric anti-reflective coating layer, to form a first opening on the dielectric anti-reflective coating layer, wherein the first opening is corresponding to the stacked structure between the adjacent capacitor holes; and removing, through etching by using the patterned dielectric anti-reflective coating layer as a mask, part of the first dielectric layer, and part of the first initial electrode layer in the first region and the second region, and removing, through etching, part of the third support layer in the first region and the second region, to expose part of a top surface of the second sacrificial layer.

6 . The method of manufacturing the semiconductor structure according to claim 5 , wherein the removing the first initial electrode layer located on the top surface of the isolation structure comprises:
removing the second sacrificial layer; removing the remaining part of the first dielectric layer; removing the first initial electrode layer covering the top surface of the third support layer and covering the top surface of the isolation structure; removing the second support layer in the first region and part of the second support layer located in the second region; and removing the first sacrificial layer, wherein a remaining part of the first initial electrode layer forms the first electrode layer.

7 . The method of manufacturing the semiconductor structure according to claim 6 , wherein the forming a dielectric layer on an inner wall of the first recess comprises:
forming an initial dielectric layer on the inner wall of the first recess, wherein the initial dielectric layer extends out of the first recess and covers the first support layer in the first region and the top surface and the sidewall of the isolation structure.

8 . The method of manufacturing the semiconductor structure according to claim 7 , wherein the forming a second electrode structure on an outer surface of the dielectric layer comprises:
forming a second initial electrode layer on the outer surface of the initial dielectric layer, wherein the second initial electrode layer in the second region forms a second recess; forming an initial buffer layer in the second recess, wherein the initial buffer layer fills up the second recess, and covers the second initial electrode layer located in the first region; and removing part of the initial dielectric layer, part of the second initial electrode layer, and part of the initial buffer layer that are located in the first region, wherein a remaining part of the second initial electrode layer and a remaining part of the initial buffer layer form the second electrode structure.

9 . The method of manufacturing the semiconductor structure according to claim 8 , wherein the method of manufacturing the semiconductor structure further comprises:
forming a second dielectric layer on the first support layer of the first region, wherein the second dielectric layer extends to the second region and covers the second electrode structure; forming spaced contact openings in the first region, wherein the contact opening exposes the top surface of the contact structure; and forming a contact plug in the contact opening.

10 . A semiconductor s

Assignees

• Changxin Memory Tech Inc
• Changxin Jidian Beijing Memory Tech Co Ltd

Inventors

• Zhu Changli
• Fang Jinguo
• Zhang Jiawei

Classifications

• H10B12/315

  with the capacitor higher than a bit line · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10B12/09

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title

• H10B12/033 Primary

  the capacitor extending over the transistor · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title