Method for processing input variables by means of a processing device comprising at least two field-effect transistors, device for executing the method, computing device, and use

Patent metadata

Field	Value
Publication number	US-12556196-B2
Application number	US-202418419789-A
Country	US
Kind code	B2
Filing date	Jan 23, 2024
Priority date	Jan 30, 2023
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A method for processing input variables using a processing device including at least two field-effect transistors. Drain-to-source paths of the at least two field-effect transistors are each connected to a first circuit node. The method includes: applying to a gate electrode of the first field-effect transistor a first drive signal which characterizes a first input variable associated with the first field-effect transistor; applying to a gate electrode of the second field-effect transistor a second drive signal which characterizes a first input variable associated with the second field-effect transistor, wherein at least one of the first drive signal and/or the second drive signal has a non-constant amplitude.

First claim

The invention claimed is:

1 . A method for processing input variables using a processing device which includes at least two field-effect transistors, wherein drain-to-source paths of the at least two field-effect transistors are each connected to a first circuit node, the method comprising the following steps:
applying to a gate electrode of the first field-effect transistor a first drive signal which characterizes a first input variable associated with the first field-effect transistor; and applying to a gate electrode of the second field-effect transistor a second drive signal which characterizes a first input variable associated with the second field-effect transistor a second drive signal; wherein at least one of the first drive signal and/or the second drive signal has a non-constant amplitude at least periodically.

2 . The method according to claim 1 , further comprising:
ascertaining an output variable based on a first variable characterizing a time curve of a summation current associated with the first circuit node, wherein the output variable characterizes a sum that has been formed based at least on the first drive signal and the second drive signal.

3 . The method according to claim 2 , wherein the ascertaining of the output variable includes at least one of the following elements:
a) converting the summation current into a first digital variable using a current-based analog/digital converter; b) converting the summation current into a first voltage by charging a capacitor using the summation current, and converting the first voltage into a second digital variable using a voltage-based analog/digital converter.

4 . The method according to claim 2 , further comprising:
starting an application of the first drive signal to the gate electrode of the first field-effect transistor and an application of the second drive signal to the gate electrode of the second field-effect transistor at a reference time; and ascertaining the output variable after a prespecifiable period of time.

5 . The method according to claim 1 , further comprising at least one of the following elements:
a) providing the first field-effect transistor with a first threshold voltage which characterizes a second input variable associated with the first field-effect transistor; b) providing the second field-effect transistor with a second threshold voltage which characterizes a second input variable associated with the second field-effect transistor; c) programming or reprogramming the first threshold voltage of the first field-effect transistor; d) programming or reprogramming the second threshold voltage of the second field-effect transistor.

6 . The method according to claim 1 , wherein at least one of the first and second field-effect transistors has a corresponding current-limiting function for limiting a current through its drain-to-source path, wherein the current-limiting function is implemented by at least one of the following elements: a) a setting of a gate voltage such that a maximum prespecifiable current through the drain-to-source path is not exceeded; b) a current-limiting element, including a resistor, or a transistor configured as a resistor.

7 . The method according to claim 1 , wherein at least one of the first drive signal and/or of the second drive signal has at least one of the following time curves at least periodically:
a) a rising stepped form, wherein the stepped form can be characterized by at least one of the following elements: a1) step width, a2) step height, a3) time offset in relation to a reference time; and b) monotonically rising.

8 . The method according to claim 7 , further comprising:
specifying a first step width for the stepped form of the first drive signal; and specifying a second step width for the stepped form of the second drive signal; wherein, the specifying of the first step width includes specifying the first step width based on the first input variable associated with the first field-effect transistor; and wherein, the specifying of the second step width includes includes specifying the second step width based on the first input variable associated with the second field-effect transistor.

9 . The method according to claim 7 , further comprising:
specifying a first slope for a rising time curve of the first drive signal; and specifying a second slope for a rising time curve of the second drive signal; wherein the specifying of the first slope includes specifying the first slope based on the first input variable associated with the first field-effect transistor, and wherein the specifying of the second slope includes specifying the second slope based on the first input variable associated with the second field-effect transistor.

10 . The method according to claim 7 , further comprising:
specifying a first logarithmic step width for the stepped form of the first drive signal, the first logarithmic step increasing logarithmically over time; and specifying an increasing, second logarithmic step width for the stepped form of the second drive signal, the second logarithmic step increasing logarithmically over time; wherein the specifying of the first logarithmic step width includes specifying the first logarithmic step width based on the first input variable associated with the first field-effect transistor; and wherein the specifying of the second logarithmic step width includes specifying the second logarithmic step width based on the first input variable associated with the second field-effect transistor.

11 . The method according to claim 1 , further comprising at least one of the following elements:
a) specifying a first time offset with respect to a reference time, for applying the first drive signal to the gate electrode of the first field-effect transistor, wherein the specifying of the first time delay includes specifying the first time delay based on the first input variable associated with the first field-effect transistor; b) specifying a second time offset in relation to the reference time for applying the second drive signal to the gate electrode of the second field-effect transistor, wherein the specifying of the second time offset includes specifying the second time offset based on the first input variable associated with the second field-effect transistor.

12 . The method according to claim 1 , further comprising:
specifying a first amplitude value for at least one of the first drive signal and/or of the second drive signal when the first input variable associated with the corresponding first and/or second field-effect transistor has a value less than a prespecifiable minimum value, wherein the first amplitude value is a prespecifiable amount, lower than a threshold voltage, of the first and/or second field-effect transistor.

13 . The method according to claim 1 , further comprising at least one of the following elements:
a) at least periodically limiting a first current through the drain-to-source path of the first field-effect transistor using a first current-limiting element including a resistor or a transistor configured as a resistor, wherein the limiting the first current through the drain-to-source path of the first field-effect transistor includes limiting the first current based on the first input variable associated with the first field-effect transistor; b) at least periodically limiting a second current through the drain-to-source path of the second field-effect transistor using a second current-limiting element including a resistor or a transistor configured as a resistor, wherein the limiting of the second current through the drain-to-source path

Assignees

• Bosch Gmbh Robert

Inventors

• Soliman Taha
• Kirchner Tobias

Classifications

• H03M1/124 Primary

  Sampling or signal conditioning arrangements specially adapted for A/D converters · CPC title

• G11C11/4023 Primary

  using field effect transistors · CPC title

• G11C11/225

  Auxiliary circuits · CPC title

• H03K5/08

  by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding (H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30) · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title