Delay circuit and semiconductor memory

Patent metadata

Field	Value
Publication number	US-12556172-B2
Application number	US-202318230096-A
Country	US
Kind code	B2
Filing date	Aug 3, 2023
Priority date	Apr 29, 2022
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

Delay circuitry includes a temperature compensation control circuit and a delay circuit. The temperature compensation control circuit is configured to generate a target temperature compensation control signal based on an initial control signal, a real-time ambient temperature signal, a temperature coefficient compensation enable signal, and a temperature coefficient control signal. The delay circuit is connected to the temperature compensation control circuit, and is configured to generate a temperature compensated target delay signal based on the target temperature compensation control signal and an initial delay signal such that a delay time of the target delay signal generated by the delay circuit can be dynamically compensated based on a real-time ambient temperature signal collected by a temperature sensor.

First claim

What is claimed is:

1 . Delay circuitry, comprising:
a temperature compensation control circuit, configured to generate a target temperature compensation control signal based on an initial control signal, a real-time ambient temperature signal, a temperature coefficient compensation enable signal, and a temperature coefficient control signal; and a delay circuit, connected to the temperature compensation control circuit and configured to generate a temperature compensated target delay signal based on the target temperature compensation control signal and an initial delay signal.

2 . The delay circuitry according to claim 1 , wherein the temperature compensation control circuit comprises:
a target temperature compensation circuit, comprising a first input terminal configured to receive the real-time ambient temperature signal, a second input terminal configured to receive the temperature coefficient compensation enable signal, a control terminal configured to receive an initial selection signal, and an output terminal configured to output a target temperature compensation signal; an addition circuit, comprising a first input terminal configured to receive the initial control signal, a second input terminal connected to the output terminal of the target temperature compensation circuit to receive the target temperature compensation signal, a carry input terminal configured to receive an initial carry signal, a first output terminal configured to output an initial temperature compensation control signal, and a carry output terminal configured to output a target carry signal; and a logic output circuit, comprising a first input terminal connected to the first output terminal of the addition circuit to receive the initial temperature compensation control signal, a second input terminal connected to the carry output terminal of the addition circuit to receive the target carry signal, and a third input terminal configured to receive the initial selection signal and output the target temperature compensation control signal through an output terminal after performing logic processing on the initial temperature compensation control signal, the target carry signal, and the initial selection signal.

3 . The delay circuitry according to claim 2 , wherein the addition circuit comprises:
N cascaded adders, wherein N>1, N is a positive integer, a carry output terminal of an adder at each stage is connected to a carry input terminal of an adder at a next adjacent stage, a carry input terminal of an adder at a first stage serves as the carry input terminal of the addition circuit and is configured to receive the initial carry signal, and a carry output terminal of an adder at a last stage serves as the carry output terminal of the addition circuit and is configured to output the target carry signal, signal output terminals of the adders at all stages jointly output sub-signals for output from the first output terminal of the addition circuit and are connected to the first input terminal of the logic output circuit, first input terminals of the adders at all stages jointly receive sub-signals received at the first input terminal of the addition circuit, and second input terminals of the adders at all stages jointly receive sub-signals received at the second input terminal of the addition circuit.

4 . The delay circuitry according to claim 3 , wherein the logic output circuit comprises:
a target overflow prevention sub-circuit, comprising a first input terminal as the third input terminal of the logic output circuit to receive the initial selection signal, and a second input terminal as the second input terminal of the logic output circuit and connected to the carry output terminal of the adder at the last stage; and N logic output sub-circuits, wherein a first input terminal of an i-th logic output sub-circuit is connected to a signal output terminal of an adder at an i-th stage, a second input terminal of each of the logic output sub-circuits is connected to a first output terminal of the target overflow prevention sub-circuit, a third input terminal of each of the logic output sub-circuits is connected to a second output terminal of the target overflow prevention sub-circuit, output terminals of the logic output sub-circuits jointly output sub-signals for output from the output terminal of the logic output circuit, first input terminals of the logic output sub-circuits jointly receive sub-signals received at the first input terminal of the logic output circuit, i∈(1, N], and i is a positive integer, wherein the target overflow prevention sub-circuit is configured to prevent an operation result of the addition circuit from overflowing.

5 . The delay circuitry according to claim 4 , wherein the target overflow prevention sub-circuit comprises:
a first NOR gate, comprising a first input terminal to receive the initial selection signal, a second input terminal connected to the carry output terminal of the adder at the last stage, and an output terminal as the first output terminal of the target overflow prevention sub-circuit and connected to the second input terminal of each of the logic output sub-circuits; and a first AND gate, comprising a first input terminal to receive the initial selection signal, a second input terminal connected to the carry output terminal of the adder at the last stage, and an output terminal as the second output terminal of the target overflow prevention sub-circuit and connected to the third input terminal of each of the logic output sub-circuits, wherein the first input terminal of the first NOR gate and the first input terminal of the first AND gate jointly receive sub-signals received at the first input terminal of the target overflow prevention sub-circuit, and the second input terminal of the first NOR gate and the second input terminal of the first AND gate jointly receive sub-signals received at the second input terminal of the target overflow prevention sub-circuit.

6 . The delay circuitry according to claim 5 , wherein each of the logic output sub-circuits comprises:
a first inverter, wherein an input terminal of the first inverter serves as the first input terminal of the logic output sub-circuit; a second NOR gate, comprising a first input terminal connected to an output terminal of the first inverter, and a second input terminal as the second input terminal of the logic output sub-circuit and connected to the output terminal of the first NOR gate; and a first OR gate, comprising a first input terminal connected to an output terminal of the second NOR gate, a second input terminal as the third input terminal of the logic output sub-circuit and connected to the output terminal of the first AND gate, and an output terminal as the output terminal of the logic output sub-circuit.

7 . The delay circuitry according to claim 4 , wherein the target temperature compensation control signal comprises N target temperature compensation control sub-signals, and the i-th logic output sub-circuit is configured to output an i-th target temperature compensation control sub-signal.

8 . The delay circuitry according to claim 7 , wherein the delay circuit comprises N target delay sub-circuits and N target logic input sub-circuits;
an input terminal of a first target delay sub-circuit is configured to receive the initial delay signal; an i-th target logic input sub-circuit comprises a first input terminal connected to an input terminal of the i-th target delay sub-circuit, a second input terminal connected to an output terminal of the i-th target delay sub-circuit, and a third input terminal configured to receive the i-th target temperature compensation control sub-signal; an output terminal of an N-th target logic input sub-circuit ser

Assignees

• Changxin Memory Tech Inc

Inventors

• Yang Yu

Classifications

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/04 Primary

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C7/1066

  Output synchronization · CPC title

• G11C7/1093

  Input synchronization · CPC title

• G11C29/50012

  of timing · CPC title