Switching converter

Patent metadata

Field	Value
Publication number	US-12556089-B2
Application number	US-202318313785-A
Country	US
Kind code	B2
Filing date	May 8, 2023
Priority date	May 8, 2023
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A switching converter is presented. The switching converter has a high side power switch coupled to a low side power switch at a switching node, a driver and a timing circuit. The driver generates a drive signal having a on-time to drive the high side power switch. The timing circuit generates a control signal to adjust the on-time during a load transient period.

First claim

The invention claimed is:

1 . A switching converter for providing an output voltage, the switching converter comprising:
a high side power switch coupled to a low side power switch at a switching node; a driver adapted to generate a drive signal to drive the high side power switch, wherein the drive signal has an on-time; and a timing circuit configured to generate a control signal to adjust the on-time during a load transient period, the control signal comprising:
a first signal for turning the high side power switch on; and
a second signal for turning the high side power switch off;
wherein the timing circuit comprises:
a first circuit adapted to generate the first signal; and
a second circuit adapted to generate the second signal, the second circuit being configured to delay assertion of the second signal until a trigger signal is asserted, so as to extend the on-time.

2 . The switching converter as claimed in claim 1 , wherein the timing circuit is adapted to increase the on-time when a load is increasing during the load transient period.

3 . The switching converter as claimed in claim 1 , wherein in a steady state the on-time remains constant.

4 . The switching converter as claimed in claim 1 , wherein the first circuit comprises a compensator circuit coupled to a first comparator, the first comparator having a first input for receiving a first dynamic reference signal from the compensator circuit, a second input for receiving an adjusted ramp signal, a first output for providing the first signal and a second output for providing a first trigger signal.

5 . The switching converter as claimed in claim 4 , wherein the first dynamic reference signal is proportional to a difference between a reference signal and the output voltage.

6 . The switching converter as claimed in claim 4 , wherein the first circuit comprises a second comparator, the second comparator having a first input for receiving a second dynamic reference signal from the compensator circuit, a second input for receiving the adjusted ramp signal, a first output for providing a third signal and a second output for providing a second trigger signal.

7 . The switching converter as claimed in claim 6 , wherein the second dynamic reference signal is proportional to a difference between a reference voltage and the output voltage.

8 . The switching converter as claimed in claim 6 , wherein during a transient load period the first dynamic reference signal and the second dynamic reference signal diverge.

9 . The switching converter as claimed in claim 1 , wherein the second circuit comprises a comparator, a capacitor circuit and a AND gate, the comparator having a first input coupled to the capacitor circuit, a second input for receiving the output voltage, and wherein the AND gate has a first input for receiving the output of the comparator, a second input for receiving the trigger signal from the first circuit, and an output for providing the second signal.

10 . The switching converter as claimed in claim 4 , comprising a ramp generator for generating the adjusted ramp signal, wherein the adjusted ramp signal comprises a feedback signal combined with a ramp signal.

11 . The switching converter as claimed in claim 10 , wherein the ramp generator comprises a synthetic ramp generator.

12 . The switching converter as claimed in claim 4 , wherein the first signal is high as long as the first dynamic reference signal is greater than the adjusted ramp signal.

13 . The switching converter as claimed in claim 6 , wherein the third signal is high as long as the second dynamic reference signal is greater than the adjusted ramp signal.

14 . The switching converter as claimed in claim 4 , wherein the compensator circuit comprises a transconductance amplifier coupled to a Type II dual compensator circuit.

15 . A method of controlling a switching converter having a high side power switch coupled to a low side power switch, the method comprising:
generating a drive signal to drive the high side power switch, wherein the drive signal has an on-time; and generating a control signal to adjust the on-time during a load transient period, wherein generating the control signal comprises:
generating, by a first circuit, a first signal for turning the high side power switch on;
generating, by a second circuit, a second signal for turning the high side power switch off; and
delaying, by the second circuit, assertion of the second signal until a trigger signal is asserted, so as to extend the on-time.

16 . The method as claimed in claim 15 , wherein, in a steady state the on-time remains constant and wherein when the load is increasing during the load transient period, the on-time is extended beyond the constant on-time.

Assignees

• Renesas Electronics Corp

Inventors

• Lalithambika Vinod Aravindakshan
• Miller Christopher John
• Warrington Allan Richard
• Labbe Benoit

Classifications

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M1/0025 Primary

  Arrangements for modifying reference values, feedback values or error values in the control loop of a converter · CPC title

• H02M3/1566

  with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation · CPC title

• H03K7/08

  Duration or width modulation {; Duty cycle modulation} · CPC title

• H03K7/06

  Frequency or rate modulation, i.e. PFM or PRM · CPC title