Pixel circuit and driving method thereof, display panel, and display device

Patent metadata

Field	Value
Publication number	US-12555539-B2
Application number	US-202418993122-A
Country	US
Kind code	B2
Filing date	May 15, 2024
Priority date	Jun 30, 2023
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A pixel circuit includes a driving sub-circuit, a compensation sub-circuit, a reset sub-circuit and a storage sub-circuit. The driving sub-circuit is configured to control a circuit brand between a second node and a third node to be closed and opened under control of a voltage of a first node. The compensation sub-circuit is configured to control a circuit branch between the first node and the third node to be closed and opened in response to a first scanning signal received at a first scanning signal terminal. The reset sub-circuit is configured to transmit a first initialization signal received at a first initialization signal terminal to the first node in response to a reset signal received at a reset signal terminal. The storage sub-circuit is configured to store voltages of the first node and the second node.

First claim

The invention claimed is:

1 . A pixel circuit, comprising:
a driving sub-circuit coupled to a first node, a second node and a third node, wherein the driving sub-circuit is configured to control a circuit branch between the second node and the third node to be closed and opened under control of a voltage of the first node; a compensation sub-circuit coupled to a first scanning signal terminal, the first node and the third node, wherein the compensation sub-circuit is configured to control a circuit branch between the first node and the third node to be closed and opened in response to a first scanning signal received at the first scanning signal terminal; a reset sub-circuit coupled to a first initialization signal terminal, a reset signal terminal and the first node, wherein the reset sub-circuit is configured to transmit a first initialization signal received at the first initialization signal terminal to the first node in response to an operating voltage of a reset signal received at the reset signal terminal; and a storage sub-circuit coupled to a first voltage signal terminal, the first node and the second node, wherein the storage sub-circuit is configured to store voltages of the first node and the second node.

2 . A driving method of a pixel circuit used to drive the pixel circuit according to claim 1 , wherein a display frame includes a refresh frame, and the refresh frame includes a first reset phase and a second reset phase; and the driving method comprises:
in the first reset phase, the reset sub-circuit transmitting the first initialization signal received at the first initialization signal terminal to the first node in response to the operating voltage of the reset signal of the reset signal terminal, and the storage sub-circuit storing a voltage of the second node after a previous frame ends; and in the second reset phase, the reset sub-circuit transmitting the first initialization signal received at the first initialization signal terminal to the first node in response to the operating voltage of the reset signal of the reset signal terminal, the compensation sub-circuit transmitting a voltage of the first node to the third node in response to an operating voltage of the first scanning signal received at the first scanning signal terminal, and the driving sub-circuit transmitting a voltage of the third node to the second node under control of the voltage of the first node.

3 . The driving method according to claim 2 , wherein the pixel circuit further includes a data writing sub-circuit coupled to a data signal terminal, a second scanning signal terminal and the second node, and the refresh frame further includes a first data writing phase and a second data writing phase; and the driving method further comprises:
in the first data writing phase, the data writing sub-circuit transmitting a data signal received at the data signal terminal to the second node in response to a first operating voltage of a second scanning signal received at the second scanning signal terminal, the driving sub-circuit transmitting a voltage of the second node to the third node under the control of the voltage of the first node, and the compensation sub-circuit transmitting a voltage of the third node to the first node in response to the operating voltage of the first scanning signal received at the first scanning signal terminal; and in the second data writing phase, the storage sub-circuit performing a discharge to transmit a stored data signal to the second node, the driving sub-circuit transmitting a voltage of the second node to the third node under the control of a voltage of the first node, and the compensation sub-circuit transmitting a voltage of the third node to the first node in response to the operating voltage of the first scanning signal received at the first scanning signal terminal.

4 . The driving method according to claim 3 , wherein the refresh frame further includes a third reset phase and a light-emitting phase, and the third reset phase is between the second data writing phase and the first light-emitting phase; and the driving method further comprises:
in the third reset phase, the data writing sub-circuit transmitting a data refresh signal received at the data signal terminal to the second node in response to a second operating voltage of the second scanning signal received at the second scanning signal terminal.

5 . The driving method according to claim 4 , wherein a time interval between a start time of the third reset phase and an end time of the second data writing phase is greater than or equal to one row scanning period, and/or a time interval between an end time of the third reset phase and a start time of the first light-emitting phase is greater than or equal to one row scanning period.

6 . The driving method according to claim 3 , wherein transistors included in the compensation sub-circuit are P-type transistors; the second reset phase includes at least 3 row scanning periods;
in the second reset phase, an operating voltage of the first scanning signal in a first row scanning period is greater than an operating voltage of the first scanning signal in a second row scanning period; and the first data writing phase is after the second reset phase and coincides with a 2N-th row scanning period after a start time of the second reset phase, wherein N≥2, and N is an integer.

7 . The driving method according to claim 2 , wherein the pixel circuit further includes a data writing sub-circuit, a leakage prevention sub-circuit and a light-emitting control sub-circuit; the pixel circuit is driven at a first refresh rate and a second refresh rate, and the second refresh rate is less than the first refresh rate; at the first refresh rate, the display frame includes the refresh frame; at the second refresh rate, the display frame includes the refresh frame and at least one holding frame; a holding frame includes a black frame insertion phase, a fourth reset phase and a second light-emitting phase; and the driving method further comprises:
in the black frame insertion phase, the light-emitting control sub-circuit controlling a circuit branch transmitting a driving current signal to be opened in response to a non-operating voltage of an enable signal received at an enable signal terminal; in the fourth reset phase, the data writing sub-circuit transmitting a data holding signal received at a data signal terminal to the second node in response to a third operating voltage of a second scanning signal received at a second scanning signal terminal; and in the second light-emitting phase, the light-emitting control sub-circuit transmitting a first voltage signal received at the first voltage signal terminal to the second node in response to an operating voltage of the enable signal received at the enable signal terminal, the driving sub-circuit generating a driving current signal based on a voltage of the first node and a voltage of the second node, the light-emitting control sub-circuit transmitting the driving current signal to a light-emitting device in response to the operating voltage of the enable signal received at the enable signal terminal; and the leakage prevention sub-circuit transmitting a constant voltage signal received at a constant voltage terminal to a fourth node in response to an operating voltage of a control signal received at a control signal terminal.

8 . The driving method according to claim 7 , wherein a time interval between an end time of the fourth reset phase and a start time of the second light-emitting phase is greater than or equal to one row scanning period.

9 . The pixel circuit according to claim 1 , further comprising:
a data writing sub-circuit coupled to a data signal termina

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Hu Ming
• Gao Wenhui
• Guo Yonglin
• Yu Ziyang
• Zhang Tiaomei
• Wang Miao
• Gu Quanyong
• Wang Shilong
• Zhang Jingwen
• Li Jian
• Wu Jianpeng
• Cheng Tianyi
• Jiang Zhiliang
• Song Gukhwan
• Zheng Hai
• Qing Haigang
• Dong Xiangdan
• Zhang Yi
• Wang Rui
• Xie Taofeng
• Qiu Haijun

Classifications

• G09G2320/0257

  Reduction of after-image effects · CPC title

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title