Masking circuit, gate driver, and display device

Patent metadata

Field	Value
Publication number	US-12555537-B2
Application number	US-202418966320-A
Country	US
Kind code	B2
Filing date	Dec 3, 2024
Priority date	Jan 23, 2024
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A masking circuit includes a ninth transistor including a control electrode connected to a second masking control node, a first electrode receiving a first clock signal, and a second electrode, a tenth transistor including a control electrode receiving a carry signal, a first electrode receiving a high gate voltage, and a second electrode connected to a first node, an eleventh transistor including a control electrode receiving a second enable signal, a first electrode connected to the first node, and a second electrode connected to the second masking control node, a twelfth transistor including a control electrode receiving a first enable signal, a first electrode connected to the second masking control node, and a second electrode connected to a second node, and a thirteenth transistor including a control electrode receiving the carry signal, a first electrode connected to the second node, and a second electrode receiving a low gate voltage.

First claim

What is claimed is:

1 . A masking circuit comprising:
a first switching element including:
a control electrode connected to a first masking control node;
a first electrode connected to a second control node; and
a second electrode connected to a third control node;
a ninth switching element including:
a control electrode connected to a second masking control node;
a first electrode which receives a first clock signal; and
a second electrode connected to the third control node;
a tenth switching element including:
a control electrode which receives a carry signal;
a first electrode which receives a high gate voltage having a relatively high level; and
a second electrode connected to a first intermediate node;
an eleventh switching element including:
a control electrode which receives a second enable signal;
a first electrode connected to the first intermediate node; and
a second electrode connected to the second masking control node;
a twelfth switching element including:
a control electrode which receives a first enable signal;
a first electrode connected to the second masking control node; and
a second electrode connected to a second intermediate node; and
a thirteenth switching element including:
a control electrode which receives the carry signal;
a first electrode connected to the second intermediate node; and
a second electrode which receives a low gate voltage having a relatively low level.

2 . The masking circuit of claim 1 , wherein the first clock signal having a relatively high level is applied to the third control node when the carry signal changes from an inactivation level to an activation level during a period in which the first enable signal has an activation level.

3 . The masking circuit of claim 1 , further comprising:
a second switching element including a control electrode which receives the carry signal, a first electrode which receives the high gate voltage, and a second electrode connected to a third intermediate node; a third switching element including a control electrode which receives the first enable signal, a first electrode connected to the third intermediate node, and a second electrode connected to the first masking control node; a fourth switching element including a control electrode which receives the second enable signal, a first electrode connected to the first masking control node, and a second electrode connected to a fourth intermediate node; and a fifth switching element including a control electrode which receives the carry signal, a first electrode connected to the fourth intermediate node, and a second electrode which receives the low gate voltage.

4 . The masking circuit of claim 3 , further comprising:
a sixth switching element including a control electrode connected to the third control node, a first electrode which receives the first clock signal, and a second electrode connected to a gate output node; a seventh switching element including a control electrode connected to a first control node, a first electrode connected to the gate output node, and a second electrode which receives the low gate voltage; and an eighth switching element including a control electrode connected to the first control node, a first electrode which receives the first clock signal, and a second electrode connected to the third control node.

5 . The masking circuit of claim 4 , wherein the first to thirteenth switching elements are P-type transistors.

6 . The masking circuit of claim 4 , further comprising:
a first masking capacitor including a first electrode which receives the first clock signal and a second electrode connected to the third control node; and a second masking capacitor including a first electrode connected to the first masking control node and a second electrode which receives the low gate voltage.

7 . The masking circuit of claim 3 , wherein a gate pulse is output from a gate output node when the first enable signal has an inactivation level during an entirety of a period in which the carry signal has an activation level, or the first enable signal changes from the inactivation level to an activation level while the carry signal has the activation level.

8 . The masking circuit of claim 3 , wherein a gate pulse is not output from a gate output node when the first enable signal has an activation level during an entirety of a period in which the carry signal has an activation level, or the first enable signal changes from the activation level to an inactivation level while the carry signal has the activation level.

9 . A gate driver comprising:
a carry generation circuit which generates a carry signal based on a previous carry signal, a first clock signal, a second clock signal, and a low gate voltage having a relatively low level; and a masking circuit connected to the carry generation circuit, the masking circuit including:
a first switching element including a control electrode connected to a first masking control node, a first electrode connected to a second control node, and a second electrode connected to a third control node;
a ninth switching element including a control electrode connected to a second masking control node, a first electrode which receives the first clock signal, and a second electrode connected to the third control node;
a tenth switching element including a control electrode which receives the carry signal, a first electrode which receives a high gate voltage having a relatively high level, and a second electrode connected to a first intermediate node;
an eleventh switching element including a control electrode which receives a second enable signal, a first electrode connected to the first intermediate node, and a second electrode connected to the second masking control node;
a twelfth switching element including a control electrode which receives a first enable signal, a first electrode connected to the second masking control node, and a second electrode connected to a second intermediate node; and
a thirteenth switching element including a control electrode which receives the carry signal, a first electrode connected to the second intermediate node, and a second electrode which receives the low gate voltage.

10 . The gate driver of claim 9 , wherein the first clock signal having a relatively high level is applied to the third control node when the carry signal changes from an inactivation level to an activation level during a period in which the first enable signal has an activation level.

11 . The gate driver of claim 9 , wherein the masking circuit further includes:
a second switching element including a control electrode which receives the carry signal, a first electrode which receives the high gate voltage, and a second electrode connected to a third intermediate node; a third switching element including a control electrode which receives the first enable signal, a first electrode connected to the third intermediate node, and a second electrode connected to the first masking control node; a fourth switching element including a control electrode which receives the second enable signal, a first electrode connected to the first masking control node, and a second electrode connected to a fourth intermediate node; and a fifth switching element including a control electrode which receives the carry signal, a first electrode connected to the fourth intermediate node, and a second electrode which receives the low gate voltage.

12 . The gate driver of claim 11 , wherein the masking circuit further includes:
a sixth switching element including a control electrode connected to the third control node, a first electrode which

Assignees

• Samsung Display Co Ltd

Inventors

• Cha Nahyeon
• Kim Kyungho
• No Sang Yong

Classifications

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• G09G3/3266

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