Display device gradually decreasing initialization voltage when converting driving frequency to low frequency

Patent metadata

Field	Value
Publication number	US-12555530-B2
Application number	US-202418748424-A
Country	US
Kind code	B2
Filing date	Jun 20, 2024
Priority date	Nov 24, 2023
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

A display device includes: a light emitting element including an anode and a cathode; a first transistor connected to the anode and a power line, and switchable by a voltage of a first node; a second transistor connected to a data line and a second node, and switchable by a write scan signal; a capacitor connected to the first node and the second node; an initialization transistor connected to the anode and an initialization line configured to receive an initialization voltage, and switchable by a bias scan signal, where the write scan signal is applied to the second transistor at a first frequency and a second frequency lower than the first frequency. When converting from the first frequency to the second frequency, in a k-th frame of the second frequency, a level of the initialization voltage may gradually decrease.

First claim

What is claimed is:

1 . A display device comprising:
a light emitting element including an anode and a cathode; a first transistor connected to the anode and a power line, and switchable by a voltage of a first node; a second transistor connected to a data line and a second node, and switchable by a write scan signal; a capacitor connected to the first node and the second node; and an initialization transistor connected to the anode and an initialization line configured to receive an initialization voltage, and switchable by a bias scan signal, wherein the write scan signal is applied to the second transistor at a first frequency and a second frequency lower than the first frequency, wherein when converting from the first frequency to the second frequency, from a start point to an end point of a k-th frame of the second frequency, a level of the initialization voltage gradually decreases, wherein k is a natural number.

2 . The display device of claim 1 , wherein in a k+1-th frame of the second frequency, the level of the initialization voltage gradually decreases.

3 . The display device of claim 2 , wherein an amount of decrease in the initialization voltage of the k-th frame is greater than an amount of decrease in the initialization voltage of the k+1-th frame.

4 . The display device of claim 3 , wherein a first voltage difference between a maximum value and a minimum value of the level of the initialization voltage in the k-th frame is greater than a second voltage difference between a maximum value and a minimum value of the level of the initialization voltage in the k+1-th frame.

5 . The display device of claim 3 , wherein the k-th frame and the k+1-th frame are adjacent to a point in time at which the first frequency is converted to the second frequency.

6 . The display device of claim 5 , wherein k is 1.

7 . The display device of claim 2 , wherein each of the k-th frame and the k+1-th frame comprises a plurality of cycle periods,
wherein the cycle periods comprise: a write cycle period during which the write scan signal and the bias scan signal are applied; and a plurality of holding cycle periods during which the write scan signal is not applied, and the bias scan signal is applied.

8 . The display device of claim 7 , wherein a level of the initialization voltage during the write cycle period of the k+1-th frame is the same as a level of the initialization voltage during the write cycle period of the k-th frame.

9 . The display device of claim 7 , wherein in each of the k-th frame and the k+1-th frame, a level of the initialization voltage during an h+1-th cycle period is lower than a level of the initialization voltage during an h-th cycle period, wherein h is a natural number.

10 . The display device of claim 7 , wherein a level of the initialization voltage during a p-th holding cycle period of the k+1-th frame is higher than a level of the initialization voltage during a p-th holding cycle period of the k-th frame, wherein p is a natural number.

11 . The display device of claim 7 , wherein in each of the k-th frame and the k+1-th frame, a level of the initialization voltage during an h+1-th cycle period is lower than or equal to a level of the initialization voltage during an h-th cycle period, wherein h is a natural number.

12 . The display device of claim 7 , wherein a level of the initialization voltage during a p-th holding cycle period of the k+1-th frame is higher than or equal to a level of the initialization voltage during a p-th holding cycle period of the k-th frame, wherein p is a natural number.

13 . The display device of claim 7 , further comprising a light emission control transistor connected to the first transistor and the anode, and switchable by a light emission signal, wherein each of the cycle periods is defined as one cycle of the light emission signal.

14 . The display device of claim 7 , wherein in the holding cycle periods of each of the k-th frame and the k+1-th frame, number of times the bias scan signal is applied per holding cycle period varies.

15 . The display device of claim 14 , wherein as an order of a holding cycle period among the holding cycle periods of each of the k-th frame and the k+1-th frame is later, the number of times the bias scan signal is applied per holding cycle period gradually increases.

16 . The display device of claim 7 , wherein in the holding cycle periods of each of the k-th frame and the k+1-th frame, a duration of an activation level of the bias scan signal varies.

17 . The display device of claim 16 , wherein as an order of a holding cycle period among the holding cycle periods of each of the k-th frame and the k+1-th frame is later, the duration of the activation level of the bias scan signal in the holding cycle period gradually increases.

18 . A display device comprising:
a light emitting element including an anode and a cathode; a first transistor connected to the anode and a power line, and switchable by a voltage of a first node; a second transistor connected to a data line and a second node, and switchable by a write scan signal; a capacitor connected to the first node and the second node; and an initialization transistor connected to the anode and an initialization line configured to receive an initialization voltage, and switchable by a bias scan signal, wherein the write scan signal is applied to the second transistor at a first frequency and a second frequency lower than the first frequency, wherein when converting from the first frequency to the second frequency, in each of a k-th frame of the second frequency and a k+1-th frame of the second frequency, a level of the initialization voltage gradually changes, and an amount of change in the initialization voltage of the k-th frame is greater than an amount of change in the initialization voltage of the k+1-th frame, wherein k is a natural number, wherein from a start point to an end point of the k-th frame of the second frequency, a level of the initialization voltage gradually decreases.

19 . The display device of claim 18 , wherein in the k+1-th frame, the level of the initialization voltage gradually decreases.

20 . The display device of claim 19 , wherein an amount of total decrease in the initialization voltage during the k-th frame is greater than an amount of total decrease in the initialization voltage during the k+1-th frame.

21 . An electronic device comprising a display device for providing images,
wherein the display device comprises: a light emitting element including an anode and a cathode; a first transistor connected to the anode and a power line, and switchable by a voltage of a first node; a second transistor connected to a data line and a second node, and switchable by a write scan signal; a capacitor connected to the first node and the second node; and an initialization transistor connected to the anode and an initialization line configured to receive an initialization voltage, and switchable by a bias scan signal, wherein the write scan signal is applied to the second transistor at a first frequency and a second frequency lower than the first frequency,
wherein when converting from the first frequency to the second frequency, from a start point to an end point of a k-th frame of the second frequency, a level of the initialization voltage gradually decreases, wherein k is a natural number.

Assignees

• Samsung Display Co Ltd

Inventors

• Park Sehyuk
• Sohn Youngha
• Yang Jin-Wook
• Lee Donggyu
• Lee Sukhun
• Jeon Jae-Hyeon

Classifications

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title