Data processing apparatus and method for transmitting triggered instructions between processing elements

Patent metadata

Field	Value
Publication number	US-12554501-B2
Application number	US-202218580865-A
Country	US
Kind code	B2
Filing date	Jun 22, 2022
Priority date	Jul 26, 2021
Publication date	Feb 17, 2026
Grant date	Feb 17, 2026

Abstract

There is provided a data processing apparatus and a method of operating a data processing apparatus. The data processing apparatus comprises a plurality of processing elements connected via a network on a single chip arranged to form a triggered spatial architecture. Each processing element comprises front end circuitry configured to generate triggered instructions which are passed to decode circuitry to cause the processing element to perform processing operations. Some processing elements are configured to operate in a producing mode in which the processing element transmits the triggered instructions as consumer instructions to be executed by each of a set of processing elements when operating in a consuming mode. Some processing elements are configured to operate in the consuming mode in which the processing elements retrieve consumer instructions transmitted from a processing element operating in a producing mode, and pass the consumer instructions to the decode circuitry.

First claim

The invention claimed is:

1 . A data processing apparatus comprising a plurality of processing elements connected via a network on a single chip arranged to form a triggered spatial architecture, each processing element of the plurality of processing elements comprising:
front end circuitry configured to process a plurality of instructions, and to generate triggered instructions, each triggered instruction generated in response to an execution state of the processing element meeting a trigger condition associated with one of the plurality of instructions; decode circuitry configured to, in response to receiving the triggered instructions, generate control signals; and execution circuitry configured to, in response to the control signals, perform processing operations and modify the execution state of the processing element, wherein: the decode circuitry is configured to, in response to a begin consuming instruction, generate begin consuming control signals to control the processing element to operate in a consuming mode; and the processing element is configured to, when operating in the consuming mode, retrieve consumer instructions transmitted from a corresponding processing element operating in a producing mode, and pass the consumer instructions to the decode circuitry as triggered instructions.

2 . The data processing apparatus of claim 1 , wherein:
the processing element further comprises consumer instruction storage circuitry to buffer the consumer instructions transmitted from the corresponding processing element operating in the producing mode; and the processing element, when operating in the consuming mode, retrieves the consumer instructions from the consumer instruction storage circuitry.

3 . The data processing apparatus of claim 2 , wherein the consumer instruction storage circuitry is a first in first out queue.

4 . The data processing apparatus of claim 2 , wherein the processing element is configured to, when the consumer instruction storage circuitry reaches capacity, transmit a consumer queue full signal to the corresponding processing element.

5 . The data processing apparatus of claim 1 , wherein the processing element is configured to, when operating in the consuming mode, cause the front end circuitry to enter a power saving state.

6 . The data processing apparatus of claim 1 , wherein the processing element is configured to, when operating in the consuming mode, detect an end consuming mode indication and, in response to detecting the end consuming mode indication, exit the consuming mode.

7 . The data processing apparatus of claim 6 , wherein the end consuming mode indication comprises an end consuming mode tag appended to a final consumer instruction transmitted by the corresponding processing element operating in the producing mode.

8 . The data processing apparatus of claim 6 , wherein the processing element is configured to, when exiting the consuming mode, perform an initialisation routine to clear data from the front end circuitry.

9 . The data processing apparatus of claim 6 , wherein:
the processing element further comprises next execution state storage to store a next execution state of the processing element; the processing element is configured to, when operating in the consuming mode and in response to detecting the end consuming mode indication, set the execution state of the circuitry to the next execution state.

10 . The data processing apparatus of claim 9 , wherein the next execution state storage is arranged as a first in first out buffer configured to store a plurality of next execution states.

11 . The data processing apparatus of claim 1 , wherein the processing element is configured to, when operating in the consuming mode, pass the consumer instructions to the decode circuitry as triggered instructions independent of the execution state of the processing element.

12 . The data processing apparatus of claim 1 , wherein:
the processing element further comprises execution state storage circuitry to store the execution state; and the front end circuitry is configured to determine, for a particular instruction, whether the execution state of the processing element meets the corresponding condition by comparing the execution state with an expected execution state corresponding to the particular instruction.

13 . A data processing apparatus comprising a plurality of processing elements connected via a network on a single chip arranged to form a triggered spatial architecture, each processing element of the plurality of processing elements comprising:
front end circuitry configured to process a plurality of instructions, and to generate triggered instructions, each triggered instruction generated in response to an execution state of the processing element meeting a trigger condition associated with one of the plurality of instructions; decode circuitry configured to, in response to receiving the triggered instructions, generate control signals; and execution circuitry configured to, in response to the control signals, perform processing operations and modify the execution state of the processing element, wherein: the decode circuitry is configured to, in response to a begin producing instruction, generate begin producing control signals to control the processing element to operate in a producing mode; and the processing element is configured to, when operating in the producing mode, transmit the triggered instructions as consumer instructions to a set of processing elements of the plurality of processing elements, the consumer instructions to be executed by each of the set of processing elements when operating in a consuming mode.

14 . The data processing apparatus of claim 13 , wherein the decode circuitry is configured to, in response to an end producing instruction, generate end producing control signals to control the processing element to cease operating in the producing mode.

15 . The data processing apparatus of claim 14 , wherein the decode circuitry is configured to, in response to the end producing instruction, transmit an end consuming mode indication to the set of processing elements.

16 . The data processing apparatus of claim 15 , wherein the end of consuming mode indication comprises an end consuming mode tag appended to a final consumer instruction transmitted to the set of processing elements.

17 . The data processing apparatus of claim 13 , wherein when in the producing mode, the processing element is configured to pause generation of triggered instructions in response to a consumer queue full signal received from one of the set of processing elements.

18 . The data processing apparatus of claim 13 , wherein:
the processing element further comprises execution state storage circuitry to store the execution state; and the front end circuitry is configured to determine, for each instruction of the plurality of instructions, whether the execution state of the processing element meets an associated trigger condition by comparing the execution state with an expected execution state corresponding to the that instruction.

19 . A data processing method for operating a data processing apparatus comprising a plurality of processing elements connected via a network on a single chip arranged to form a triggered spatial architecture, each processing element comprising front end circuitry, decode circuitry, and execution circuitry, the method comprising:
processing, using the front end circuitry a plurality of instructions, and generating t

Assignees

• Advanced Risc Mach Ltd

Inventors

• VENU Balaji
• Eyole Mbou
• Gabrielli Giacomo

Classifications

• G06F9/3016

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F9/38 Primary

  Concurrent instruction execution, e.g. pipeline or look ahead · CPC title

• G06F15/80 Primary

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F15/173

  using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake · CPC title