Manufacturing method of displaying base plate, displaying base plate and displaying apparatus

Patent metadata

Field	Value
Publication number	US-12550756-B2
Application number	US-202117762239-A
Country	US
Kind code	B2
Filing date	May 24, 2021
Priority date	May 24, 2021
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A manufacturing method of a displaying base plate, a displaying base plate and a displaying apparatus. The displaying base plate includes an active area and a peripheral area located at a periphery of the active area. The displaying base plate includes: a substrate; a wiring functional layer disposed on one side of the substrate, wherein the wiring functional layer includes a metal wiring and bonding terminals connected to the metal wiring), the bonding terminals include a first bonding terminal, a second bonding terminal and a third bonding terminal, the first bonding terminal and the second bonding terminal are located at the active area, and the third bonding terminal is located at the peripheral area; a first passivation layer disposed on one side of the wiring functional layer that is away from the substrate; and a light shielding layer disposed on one side of the first passivation layer that is away from the substrate.

First claim

The invention claimed is:

1 . A displaying base plate, including an active area and a peripheral area located at a periphery of the active area, wherein the displaying base plate comprises:
a substrate; a wiring functional layer disposed on one side of the substrate, wherein the wiring functional layer comprises metal wirings and bonding terminals connected to the metal wirings, the bonding terminals comprise a first bonding terminal, the first bonding terminal is configured for bonding an LED chip, and the first bonding terminal is located at the active area; a first passivation layer disposed on one side of the wiring functional layer that is away from the substrate; and a light shielding layer disposed on one side of the first passivation layer that is away from the substrate, wherein an orthographic projection of the light shielding layer on the substrate and orthographic projections of the bonding terminals on the substrate do not overlap, and in the active area, the orthographic projection of the light shielding layer on the substrate at least partially covers orthographic projections of the metal wirings on the substrate, and an orthographic projection of the first passivation layer on the substrate and the orthographic projections of the bonding terminals on the substrate do not overlap.

2 . The displaying base plate according to claim 1 , wherein in the active area, the orthographic projection of the light shielding layer on the substrate and the orthographic projections of the metal wirings on the substrate completely coincide.

3 . The displaying base plate according to claim 1 , wherein the wiring functional layer comprises: a first metal layer, an insulating layer and a second metal layer that are disposed in stack, and the first metal layer is disposed closer to the substrate;
the bonding terminals further comprise a second bonding terminal and a third bonding terminal, the second bonding terminal is configured for bonding a driving chip, the driving chip is configured for driving the LED chip to emit light, the third bonding terminal is configured for bonding a flexible circuit board, the second bonding terminal is located at the active area, and the third bonding terminal is located at the peripheral area; and the metal wiring comprises a first metal wiring located at the first metal layer and a second metal wiring located at the second metal layer, the bonding terminals are located at the second metal layer and are interconnected with the second metal wiring, and the second metal wiring and the first metal wiring are connected by a via hole disposed in the insulating layer.

4 . The displaying base plate according to claim 3 , wherein the second metal layer is a copper layer, a transparent electrode layer is disposed between the first passivation layer and the second metal layer, and an orthographic projection of the transparent electrode layer on the substrate covers an orthographic projection of the third bonding terminal on the substrate.

5 . The displaying base plate according to claim 3 , wherein the second metal layer comprises a copper layer and a copper-nickel-alloy layer disposed on one side of the copper layer that is away from the substrate, and a thickness of the first passivation layer is greater than or equal to 8000 angstroms.

6 . The displaying base plate according to claim 5 , wherein an orthographic projection of the copper-nickel-alloy layer on the substrate covers an orthographic projection of the copper layer on the substrate.

7 . The displaying base plate according to claim 4 , wherein a first planarization layer is disposed on one side of the light shielding layer that is away from the substrate, and an orthographic projection of the first planarization layer on the substrate and the orthographic projections of the bonding terminals on the substrate do not overlap.

8 . The displaying base plate according to claim 4 , wherein a second planarization layer is disposed between the light shielding layer and the first passivation layer, and an orthographic projection of the second planarization layer on the substrate and the orthographic projections of the bonding terminals on the substrate do not overlap.

9 . The displaying base plate according to claim 8 , wherein a second passivation layer is disposed between the light shielding layer and the second planarization layer, and an orthographic projection of the second passivation layer on the substrate and the orthographic projections of the bonding terminals on the substrate do not overlap.

10 . The displaying base plate according to claim 3 , wherein the insulating layer comprises a third passivation layer, a third planarization layer and a fourth passivation layer that are disposed in stack on one side of the first metal layer that is away from the substrate, and the third passivation layer is disposed closer to the first metal layer.

11 . The displaying base plate according to claim 3 , wherein an electroplating functional layer is disposed between the substrate and the first metal layer, and an orthographic projection of the electroplating functional layer on the substrate and an orthographic projection of the first metal layer on the substrate completely coincide.

12 . The displaying base plate according to claim 3 , wherein the active area comprises a plurality of pixel units that are arranged in an array, and the first metal wiring comprises:
at least one first sub-wiring extending in a pixel column direction in the active area, wherein the first sub-wiring has a first line width in a pixel row direction; and at least one second sub-wiring extending in the pixel column direction in the active area, wherein the second sub-wiring has a second line width in the pixel row direction, and the second line width is less than the first line width.

13 . The displaying base plate according to claim 12 , wherein a second sub-wiring adjacent to a first sub-wiring in the pixel row direction and the first sub-wiring have a first spacing therebetween, wherein the first spacing is greater than three times the first line width.

14 . The displaying base plate according to claim 12 , wherein an orthographic projection of the first bonding terminal on the substrate is located in an area of an orthographic projection of the first sub-wiring on the substrate.

15 . A displaying apparatus, wherein the displaying apparatus comprises the displaying base plate according to claim 1 .

16 . A manufacturing method of a displaying base plate, wherein the displaying base plate comprises an active area and a peripheral area located at a periphery of the active area, and the manufacturing method comprises:
providing a substrate; forming a wiring functional layer on one side of the substrate, wherein the wiring functional layer comprises a metal wiring and bonding terminals connected to the metal wiring, the bonding terminals comprise a first bonding terminal, the first bonding terminal is configured for bonding an LED chip, and the first bonding terminal is located at the active area; and forming sequentially a first passivation layer and a light shielding layer on one side of the wiring functional layer that is away from the substrate, wherein an orthographic projection of the light shielding layer on the substrate and orthographic projections of the bonding terminals on the substrate do not overlap, and in the active area, the orthographic projection of the light shielding layer on the substrate at least partially covers orthographic projections of the metal wirings on the substrate, and an orthographic projection of

Assignees

• Boe Technology Group Co Ltd

Inventors

• Yue Yang
• Shu Shi
• Yao Qi
• Yu Yong
• Li Shipei
• Li Xiang
• Xu Chuanxiang
• Liu Wenqu
• Gu Renquan
• Huang Haitao

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10D86/00

  Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title