Method of forming an integrated circuit via

Patent metadata

Field	Value
Publication number	US-12550650-B2
Application number	US-202217888057-A
Country	US
Kind code	B2
Filing date	Aug 15, 2022
Priority date	Aug 16, 2021
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A method of forming a via is provided. A lower metal element is formed, and a first patterned photoresist is used to form a sacrificial element over the lower metal element. A dielectric region including a dielectric element projection extending upwardly above the sacrificial element is formed. A second patterned photoresist including a second photoresist opening is formed, wherein the dielectric element projection is at least partially located in the second photoresist opening. A dielectric region trench opening is etched in the dielectric region. The sacrificial element is removed to define a via opening extending downwardly from the dielectric region trench opening. The dielectric region trench opening and the via opening are filled to define (a) an upper metal element in the dielectric region trench opening and (b) a via in the via opening, wherein the via extends downwardly from the upper metal element.

First claim

The invention claimed is:

1 . A method, comprising:
depositing a sacrificial material layer over an integrated circuit structure; forming a first photoresist layer over the sacrificial material layer; patterning the first photoresist layer to define a first photoresist element; etching the sacrificial material layer to form a sacrificial element below the first photoresist element; depositing a dielectric region including a dielectric element projection extending upwardly above the sacrificial element; forming a second photoresist layer; patterning the second photoresist layer to form a second photoresist opening in the second photoresist layer, wherein at least a portion of the dielectric element projection extends upwardly in the second photoresist opening, wherein an alignment of the second photoresist opening relative to the dielectric element projection defines an interference area between the second photoresist layer and the dielectric element projection, and wherein the second photoresist layer is physically excluded from the interference area by the dielectric element projection; etching through the second photoresist opening to form a dielectric region trench opening in the dielectric region; removing the sacrificial element to define a via opening extending below the dielectric region trench opening; and filling the dielectric region trench opening and the via opening to define (a) a metal element in the dielectric region trench opening and (b) a via in the via opening, wherein the via extends downwardly from the metal element.

2 . The method of claim 1 , wherein patterning the first photoresist layer to define the first photoresist element comprises using a bright field photomask to pattern the first photoresist layer.

3 . The method of claim 1 , wherein:
the first photoresist element comprises a vertically-extending photoresist pillar; and the sacrificial element comprises a vertically-extending sacrificial pillar.

4 . The method of claim 1 , wherein the sacrificial element is laterally misaligned with the second photoresist opening.

5 . The method of claim 3 , wherein a perimeter of the sacrificial element extends laterally beyond a perimeter of the second photoresist opening.

6 . The method of claim 1 , comprising filling the dielectric region trench opening and the via opening using a dual damascene process.

7 . The method of claim 1 , wherein the sacrificial material layer comprises polyimide.

8 . The method of claim 1 , wherein the sacrificial material layer comprises nitride, polysilicon, or aluminum.

9 . The method of claim 1 , comprising etching the sacrificial element to reduce a lateral width of the sacrificial element before depositing the dielectric region.

10 . The method of claim 1 , comprising:
forming an anti-reflective coating over the dielectric region, the anti-reflective coating including a cap portion covering an upper portion of the dielectric element projection; forming the second photoresist layer over the anti-reflective coating; after patterning the second photoresist layer to form the second photoresist opening, removing the cap portion of the anti-reflective coating; and removing at least a partial vertical height of the dielectric element projection.

11 . The method of claim 1 , wherein the dielectric element projection projects upwardly higher than a top surface of the second photoresist layer.

12 . The method of claim 1 , wherein the deposited dielectric region encloses the sacrificial element.

13 . A method, comprising:
forming a lower metal element; using a first patterned photoresist to form a sacrificial element over the lower metal element; forming a dielectric region including a dielectric element projection extending upwardly above the sacrificial element; forming a second patterned photoresist including a second photoresist opening, wherein at least a portion of the dielectric element projection extends upwardly in the second photoresist opening, wherein an alignment of the second photoresist opening relative to the dielectric element projection defines an interference area between the second photoresist layer and the dielectric element projection, and wherein the second photoresist layer is physically excluded from the interference area by the dielectric element projection; etching a dielectric region trench opening in the dielectric region; removing the sacrificial element to define a via opening extending downwardly from the dielectric region trench opening; and filling the dielectric region trench opening and the via opening to define (a) an upper metal element in the dielectric region trench opening and (b) a via in the via opening, wherein the via extends downwardly from the upper metal element.

14 . The method of claim 13 , wherein using a first patterned photoresist to form the sacrificial element over the lower metal element comprises:
patterning a first photoresist using a bright field photomask to define a first photoresist element; and etching the sacrificial material layer to form a sacrificial element below the first photoresist element.

15 . The method of claim 13 , comprising filling the dielectric region trench opening and the via opening using a dual damascene process.

16 . The method of claim 13 , comprising:
forming an anti-reflective coating over the dielectric region, the anti-reflective coating including a cap portion covering an upper portion of the dielectric element projection; forming the second photoresist layer over the anti-reflective coating; after forming the second patterned photoresist including the second photoresist opening, removing the cap portion of the anti-reflective coating; and removing at least a partial vertical height of the dielectric element projection.

17 . The method of claim 13 , wherein a perimeter of the sacrificial element extends laterally beyond a perimeter of the second photoresist opening.

18 . A method, comprising:
forming a sacrificial material layer in an integrated circuit structure; using a bright field photomask to define a first photoresist element over the sacrificial material layer; etching the sacrificial material layer to form a sacrificial element below the first photoresist element, forming a dielectric region over the sacrificial material layer, the dielectric region including a dielectric element projection extending upwardly above the sacrificial element; forming a second patterned photoresist including a second photoresist opening, wherein at least a portion of the dielectric element projection extends upwardly in the second photoresist opening wherein an alignment of the second photoresist opening relative to the dielectric element projection defines an interference area between the second photoresist layer and the dielectric element projection, and wherein the second photoresist layer is physically excluded from the interference area by the dielectric element projection; etching through the second photoresist opening to form a dielectric region trench opening in the dielectric region, the dielectric region trench opening exposing a portion of a surface of the sacrificial element; removing the sacrificial element to define a via opening; and filling the dielectric region trench opening and the via opening to define (a) an upper metal element in the dielectric region trench opening and (b) a via in the via opening.

19 . The method of claim 18 , comprising:
forming the sacrificial material layer over a lower metal element;

Assignees

• Microchip Tech Inc

Inventors

• Baker Daniel
• Sato Justin
• Sundahl Chris

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/084 Primary

  for dual-damascene structures · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title