Display substrate, manufacturing method thereof and display device

Patent metadata

Field	Value
Publication number	US-12550440-B2
Application number	US-202218015511-A
Country	US
Kind code	B2
Filing date	Feb 24, 2022
Priority date	Feb 24, 2022
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A display substrate includes a base substrate, the base substrate including a display region, and the display region including a plurality of pixel regions; and at least four conductive layers arranged in a stacked manner, located on the base substrate, wherein any two adjacent conductive layers are arranged in an insulated manner, each of the conductive layers includes conductive patterns located in the pixel regions, the conductive patterns of any two adjacent conductive layers in the same pixel region form a storage capacitor (e.g., Cst1, Cst2 and Cst3), and in a direction perpendicular to the base substrate, projections of the at least four conductive layers on the base substrate overlap. A manufacturing method of a display substrate and a display device are further provided.

First claim

What is claimed is:

1 . A display substrate, comprising:
a base substrate, comprising a display region, the display region comprising a plurality of pixel regions; and at least four conductive layers arranged in a stacked manner on the base substrate, wherein any two adjacent conductive layers are arranged in an insulated manner, each of the conductive layers comprises conductive patterns located in the pixel regions, the conductive patterns of any two adjacent conductive layers in a same pixel region form a storage capacitor, and in a direction perpendicular to the base substrate, projections of the at least four conductive layers on the base substrate overlap with each other; wherein the at least four conductive layers comprise a first conductive layer, a second conductive layer, a third conductive layer and a pixel electrode layer, wherein the first conductive layer comprises a first conductive pattern, the second conductive layer comprises a second conductive pattern, the third conductive layer comprises a third conductive pattern, and the pixel electrode layer comprises pixel electrodes; and the first conductive pattern and the second conductive pattern form a first storage capacitor, the second conductive pattern and the third conductive pattern form a second storage capacitor, the third conductive pattern and the pixel electrodes form a third storage capacitor, the first conductive pattern is electrically connected with the third conductive pattern, and the second conductive pattern is electrically connected with the pixel electrodes.

2 . The display substrate according to claim 1 , further comprising a first insulating layer, a second insulating layer and a third insulating layer, wherein the first insulating layer is between the first conductive layer and the second conductive layer, the second insulating layer is between the second conductive layer and the third conductive layer, and the third insulating layer is between the third conductive layer and the pixel electrode layer.

3 . The display substrate according to claim 2 , wherein the second insulating layer and the third insulating layer comprise through holes arranged in a penetrating manner, and the pixel electrodes are electrically connected with the second conductive pattern via the through holes.

4 . The display substrate according to claim 3 , wherein the third conductive pattern comprises hollowed-out structures, and an orthographic projection of the hollowed-out structures on the base substrate covers an orthographic projection of the through holes on the base substrate.

5 . The display substrate according to claim 1 , wherein the base substrate further comprises a non-display region surrounding the display region;
the first conductive layer further comprises a first connection line, the first connection line extends in a first direction, and the first connection line and the first conductive pattern are integrally arranged; the third conductive layer further comprises a second connection line, the second connection line extends in a second direction, the second connection line and the third conductive pattern are integrally arranged, and the second direction intersects the first direction; and the pixel electrode layer further comprises a wire located in the non-display region, and the wire surrounds the display region and is electrically connected with the first connection line and the second connection line.

6 . The display substrate according to claim 1 , further comprising transistors located in the pixel regions, wherein gates of the transistors are on the first conductive layer, and first electrodes and second electrodes of the transistors are on the second conductive layer.

7 . The display substrate according to claim 6 , wherein the third conductive layer is metal, and an orthographic projection of the third conductive pattern on the base substrate at least covers an orthographic projection of channel regions of the transistors on the base substrate.

8 . The display substrate according to claim 6 , wherein an orthographic projection of the first conductive pattern on the base substrate surrounds half of an orthographic projection of the transistors on the base substrate.

9 . The display substrate according to claim 6 , wherein an orthographic projection of the second conductive pattern on the base substrate overlaps the orthographic projection of the first conductive pattern on the base substrate, and the second conductive pattern and the first electrodes of the transistors are integrally arranged.

10 . The display substrate according to claim 6 , wherein an orthographic projection of the pixel electrodes on the base substrate covers the orthographic projection of the transistors on the base substrate.

11 . A display device, comprising a display substrate and an opposite substrate disposed opposite to each other and a dimming layer located between the display substrate and the opposite substrate;
wherein the display substrate comprises: a base substrate, comprising a display region, the display region comprising a plurality of pixel regions; and at least four conductive layers arranged in a stacked manner on the base substrate, wherein any two adjacent conductive layers are arranged in an insulated manner, each of the conductive layers comprises conductive patterns located in the pixel regions, the conductive patterns of any two adjacent conductive layers in a same pixel region form a storage capacitor, and in a direction perpendicular to the base substrate, projections of the at least four conductive layers on the base substrate overlap with each other; wherein the at least four conductive layers comprise a first conductive layer, a second conductive layer, a third conductive layer and a pixel electrode layer, wherein the first conductive layer comprises a first conductive pattern, the second conductive layer comprises a second conductive pattern, the third conductive layer comprises a third conductive pattern, and the pixel electrode layer comprises pixel electrodes; and the first conductive pattern and the second conductive pattern form a first storage capacitor, the second conductive pattern and the third conductive pattern form a second storage capacitor, the third conductive pattern and the pixel electrodes form a third storage capacitor, the first conductive pattern is electrically connected with the third conductive pattern, and the second conductive pattern is electrically connected with the pixel electrodes.

12 . The display device according to claim 11 , wherein the opposite substrate comprises a common electrode, and the common electrode, a first conductive pattern and a third conductive pattern load a same electric signal.

13 . The display device according to claim 11 , wherein the dimming layer is an electrophoresis layer or a liquid crystal layer.

14 . A method for manufacturing the display substrate according to claim 1 , comprising:
providing a base substrate, the base substrate comprising a display region, and the display region comprising a plurality of pixel regions; and forming at least four conductive layers arranged in a stacked manner on the base substrate, wherein any two adjacent conductive layers are arranged in an insulated manner, each of the conductive layers comprises conductive patterns located in the pixel regions, the conductive patterns of any two adjacent conductive layers in a same pixel region form a storage capacitor, and in a direction perpendicular to the base substrate, projections of the at least four conductive layers on the base substrate overlap with each other.

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Wang Min
• Wang Zhe
• Hua Gang
• Deng Liguang
• Wang Dong
• Li Shaobo
• Hu Jintang
• Liu Jinghao
• Su Shaokai
• Pan Liangliang
• Bai Jiahao
• Lin Zhining
• Chen Xinyu
• Qi Zixi
• Zhang Pengqu

Classifications

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• G02F1/167

  by electrophoresis · CPC title

• G02F1/1368 Primary

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/136213

  Storage capacitors associated with the pixel electrode · CPC title