Array substrate, display panel and display device including non-display area electrically connected power signal lines

Patent metadata

Field	Value
Publication number	US-12550434-B2
Application number	US-202217683495-A
Country	US
Kind code	B2
Filing date	Mar 1, 2022
Priority date	Mar 27, 2020
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

An array substrate includes a light-transmitting area, a non-display area around the light-transmitting area, and a display area around the non-display area. The display area includes power signal lines. The power signal lines include first power signal lines and second power signal lines. The first power signal lines extend to the non-display area, and the second power signal lines are disposed around the light-transmitting area through the non-display area, and are electrically connected to the first power signal lines in the non-display area.

First claim

What is claimed is:

1 . An array substrate, comprising:
a light-transmitting area; a non-display area around the light-transmitting area; a display area around the non-display area; a plurality of data lines; and a capacitive layer; wherein the display area comprises a plurality of power signal lines which comprises a plurality of first power signal lines and a plurality of second power signal lines, the plurality of first power signal lines extends in a first direction, the plurality of second power signal lines extends in a second direction, the plurality of first power signal lines extends to the non-display area, the plurality of second power signal lines is disposed around the light-transmitting area through the non-display area, and is electrically connected to the plurality of first power signal lines in the non-display area, the first direction intersects with the second direction, the plurality of second power signal lines is disposed in the capacitive layer, the plurality of first power signal lines is disposed in a same layer as the plurality of data lines; or the plurality of second power signal lines is disposed in a same layer as the plurality of data lines, and the plurality of first power signal lines is disposed in the capacitive layer.

2 . The array substrate of claim 1 , wherein the plurality of first power signal lines and the plurality of second power signal lines form a grid structure in the non-display area and are electrically connected through overlapping parts of the grid structure.

3 . The array substrate of claim 2 , wherein the plurality of first power signal lines comprises a plurality of first sub-power signal lines and a plurality of second sub-power signal lines; the plurality of first sub-power signal lines and the plurality of second sub-power signal lines are respectively disposed on two sides of the light-transmitting area in the first direction; at least one of the plurality of first sub-power signal lines or the plurality of second sub-power signal lines extend to the non-display area and form a mesh structure with the plurality of second power signal lines in the non-display area, wherein the first direction is a direction in which the plurality of data lines of the array substrate extend, and the second direction is a direction in which a plurality of scanning lines of the array substrate extend.

4 . The array substrate of claim 3 , wherein the plurality of data lines comprise a plurality of first data lines, the plurality of first data lines comprise a plurality of first sub-data lines, a plurality of second sub-data lines, and a plurality of third sub-data lines; the plurality of first sub-data lines and the plurality of third sub-data lines are respectively disposed on two sides of the light-transmitting area in the first direction, the plurality of second sub-data lines are disposed around the non-display area, and the plurality of first sub-data lines are electrically connected to the plurality of third sub-data lines through the plurality of second sub-data lines; for one of the plurality of first sub-power signal lines, one of the plurality of first sub-data lines and one of the plurality of second sub-data lines that are provided for a same column of pixel units, an extension end of the one of the plurality of first sub-power signal lines and an intersection point of the one of the plurality of first sub-data lines and the one of the plurality of second sub-data lines are in a same line in the second direction, and/or for one of the plurality of second sub-power signal lines, one of the plurality of third sub-data lines and one of the plurality of second sub-data lines that are provided for a same column of pixel units, an extension end of the one of the plurality of second sub-power signal lines and an intersection point of the one of the plurality of third sub-data lines and the one of the plurality of second sub-data lines are in a same line in the second direction.

5 . The array substrate according to claim 2 , wherein the plurality of first power signal lines comprise a plurality of first sub-power signal lines and a plurality of second sub-power signal lines; the plurality of first sub-power signal lines and the plurality of second sub-power signal lines are respectively disposed on two sides of the light-transmitting area along the first direction; at least one of the plurality of first sub-power signal lines or the plurality of second sub-power signal lines extend to the non-display area and form a mesh structure with the plurality of second power signal lines in the non-display area, wherein the first direction is a direction in which a plurality of scanning lines of the array substrate extend, and the second direction is a direction in which the plurality of data lines of the array substrate extend.

6 . The array substrate of claim 5 , wherein the plurality of scanning lines comprise a plurality of first scanning lines, the plurality of first scanning lines comprise a plurality of first sub-scanning lines, a plurality of second sub-scanning lines, and a plurality of third sub-scanning lines; the plurality of first sub-scanning lines and the plurality of second sub-scanning lines are disposed on two sides of the light-transmitting area in the first direction, the plurality of second sub-scanning lines are disposed around the non-display area, and the plurality of first sub-scanning lines are electrically connected to the plurality of third sub-scanning lines through the plurality of second sub-scanning lines; for one of the plurality of first sub-power signal lines, one of the plurality of first sub-scanning lines and one of the plurality of second sub-scanning lines that are provided for a same row of pixel units, an extension end of the one of the plurality of first sub-power signal lines and an intersection point of the one of the plurality of first sub-scanning lines and the one of the plurality of second sub-scanning lines are in a same line in the second direction, and/or for one of the plurality of second sub-power signal lines, one of the plurality of third sub-scanning lines and one of the plurality of second sub-scanning lines that are provided for a same row of pixel units, an extension end of the one of the plurality of second sub-power signal lines and an intersection point of the one of the plurality of third sub-scanning lines and the one of the plurality of second sub-scanning lines are in a same line in the second direction.

7 . The array substrate of claim 1 , wherein the light-transmitting area is a through-hole area, and the array substrate has a through hole in the light-transmitting area.

8 . The array substrate of claim 1 , wherein the display area includes a first display area and a second display area, the first display area is on a side of the light-transmitting area facing away from a side into which power signals flow, and the second display area is in the display area other than the first display area.

9 . The array substrate of claim 4 , wherein the plurality of first power signal lines and the plurality of first data lines are disposed at intervals in the second direction.

10 . The array substrate of claim 4 , wherein each column of pixel units is electrically connected to a respective one of the plurality of first power signal lines and a respective one of the plurality of first data lines, the respective one of the plurality of first power signal lines provides a power signal for the each column of pixel units, and the respective one of the plurality of first data lines provides a data signal for the column of pixel units.

11 . The array substrate of claim 6 , wherein the plurality of first power signal

Assignees

• Kunshan Govisionox Optoelectronics Co Ltd

Inventors

• Xu Chuanzhi
• Zhang Lu
• Hu Siming
• Han Zhenzhen

Classifications

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D86/411

  characterised by materials, geometry or structure of the substrates · CPC title

• G09F9/00 Primary

  Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements (in which the variable information is permanently attached to a movable support G09F11/00; abacus G06C1/00; slide-rules G06G1/00) · CPC title