Display substrate and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12550429-B2
Application number	US-202117555201-A
Country	US
Kind code	B2
Filing date	Dec 17, 2021
Priority date	Mar 23, 2021
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

The present application provides a display substrate and a method for manufacturing the same. The display substrate includes: a base substrate; and at least two layers of pixel circuits on the base substrate. The at least two layers of pixel circuits include a first-layer pixel circuit and a second-layer pixel circuit which are in different layers; the first-layer pixel circuit includes a plurality of first thin film transistors; the second-layer pixel circuit includes a plurality of second thin film transistors; and an orthographic projection of at least one first thin film transistor onto the base substrate at least partially overlaps an orthographic projection of at least one second thin film transistor onto the base substrate.

First claim

What is claimed is:

1 . A display substrate, comprising:
a base substrate; and at least two layers of different pixel circuits on the base substrate; wherein the at least two layers of different pixel circuits include a first-layer pixel circuit and a second-layer pixel circuit which are in different layers; the first-layer pixel circuit includes a plurality of first thin film transistors; the second-layer pixel circuit includes a plurality of second thin film transistors; and an orthographic projection of at least one first thin film transistor onto the base substrate at least partially overlaps an orthographic projection of at least one second thin film transistor onto the base substrate; wherein the first-layer pixel circuit and the second-layer pixel circuit are electrically coupled to pixel electrodes of different sub-pixels.

2 . The display substrate according to claim 1 , wherein
at least two of the first thin film transistors are different types of thin film transistors with active layers of different materials, or all of the first thin film transistors are the same type of thin film transistors with the active layers of the same material; at least two of the second thin film transistors are different types of thin film transistors with active layers of different materials, or all of the second thin film transistors are the same type of thin film transistors with the active layers of the same material; and at least one of the first thin film transistors and at least one of the second thin film transistors are different types of thin film transistors with active layers of different materials, or, at least one of the first thin film transistors and at least one of the second thin film transistors are the same type of thin film transistors with the active layers of the same material.

3 . The display substrate according to claim 2 , wherein
at least one of the first thin film transistors is at least one of a metal oxide thin film transistor with a metal oxide active layer, a low temperature polysilicon thin film transistor with a low temperature polysilicon active layer, and an amorphous silicon thin film transistor with an amorphous silicon active layer; at least one of the second thin film transistors is at least one of a metal oxide thin film transistor with a metal oxide active layer, a low temperature polysilicon thin film transistor with a low temperature polysilicon active layer, and an amorphous silicon thin film transistor with an amorphous silicon active layer.

4 . The display substrate according to claim 3 , wherein
the display substrate includes at least three sub-pixels; the at least three sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel; each sub-pixel is provided with a corresponding pixel electrode; the pixel electrode of at least one first sub-pixel is coupled to at least one first thin film transistor having an oxide active layer or an amorphous silicon active layer, or coupled to at least one second thin film transistor having an oxide active layer or an amorphous silicon active layer; the pixel electrode of at least one second sub-pixel is coupled to at least one first thin film transistor having an oxide active layer or an amorphous silicon active layer, or coupled to at least one second thin film transistor having an oxide active layer or an amorphous silicon active layer; and the pixel electrode of at least one third sub-pixel is coupled to at least one first thin film transistor having a low-temperature polysilicon active layer, or coupled to at least one second thin film transistor having a low-temperature polysilicon active layer.

5 . The display substrate according to claim 3 , wherein the first sub-pixel is a green sub-pixel, the second sub-pixel is a blue sub-pixel and the third sub-pixel is a red sub-pixel.

6 . The display substrate according to claim 5 , wherein each first thin film transistor in the first-layer pixel circuit is a metal oxide thin film transistor or an amorphous silicon thin film transistor; each second thin film transistor in the second-layer pixel circuit is a low-temperature polysilicon thin film transistor; each of the pixel electrodes of the first sub-pixel and the second sub-pixel is coupled to the corresponding first thin film transistor in the first-layer pixel circuit; and the pixel electrode of the third sub-pixel is coupled to the corresponding second thin film transistor in the second-layer pixel circuit.

7 . The display substrate according to claim 6 , wherein the first thin film transistor and the second thin film transistor are both NMOS transistors.

8 . The display substrate according to claim 3 , wherein the first thin film transistor is coupled to the pixel electrode in the corresponding sub-pixel through a first via-hole; and the second thin film transistor is coupled to the pixel electrode in the corresponding sub-pixel through a second via-hole;
an orthographic projection of the first thin film transistor onto the base substrate and an orthographic projection of the second thin film transistor onto the base substrate at least partially do not overlap each other, with a non-overlapping area defined between the orthographic projection of the first thin film transistor onto the base substrate and the orthographic projection of the second thin film transistor onto the base substrate; the first via-hole and the second via-hole are both located in the non-overlapping area; and an orthographic projection of the first via-hole onto the base substrate does not overlap an orthographic projection of the second via-hole onto the base substrate.

9 . The display substrate according to claim 8 , wherein the first via-hole and the second via-hole are located at two sides of the non-overlapping area.

10 . The display substrate according to claim 1 , wherein the display substrate includes two opposite sides; one of the two opposite sides is provided with a first gate driving circuit, and the other one of the two opposite sides is provided with a second gate driving circuit; the first-layer pixel circuit is coupled to the first gate driving circuit, and the second-layer pixel circuit is coupled to the second gate driving circuit; and the first gate driving circuit and the second gate driving circuit are independent of each other.

11 . The display substrate according to claim 10 , wherein the first gate driving circuit and the second gate driving circuit are gate driver on array (GOA) driving circuits or a gate chip on flex/film (COF) driving circuits.

12 . The display substrate according to claim 1 , wherein the display substrate specifically includes:
a buffer layer on the base substrate; wherein the first-layer pixel circuit is on the buffer layer, and the first thin film transistor in the first-layer pixel circuit includes: a first active layer, a first gate electrode, a first source electrode and a first drain electrode; a first gate insulating layer located between the first active layer and the first gate electrode; a first interlayer dielectric layer located between the first gate electrode and the first source electrode together with the first drain electrode; a base layer located on the first-layer pixel circuit, wherein the base layer is an organic insulating layer or an inorganic insulating layer; wherein the second-layer pixel circuit is located on the base layer, and the second thin film transistor in the second-layer pixel circuit includes: a second active layer, a second gate electrode, a second source electrode and a second drain electrode; a second gate insulating layer located between the second active layer and the second gate electrode;

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhang Zhen
• Li Fuqiang
• Wang Hongrun

Classifications

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/471 Primary

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/421

  having a particular composition, shape or crystalline structure of the active layer · CPC title