Semiconductor device and method of fabricating a semiconductor device

Patent metadata

Field	Value
Publication number	US-12550422-B2
Application number	US-202318121293-A
Country	US
Kind code	B2
Filing date	Mar 14, 2023
Priority date	Mar 24, 2022
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

In an embodiment, a semiconductor device is provided that includes: a vertical power FET configured to switch a load current and provide a channel of a first conductivity type; and a lateral FET configured to drive the vertical power FET and provide a channel of a second conductivity type opposing the first conductivity type. The vertical power FET and the lateral FET are monolithically integrated into a semiconductor substrate of the first conductivity type and a drain of the lateral FET is electrically coupled to a gate of the vertical power FET.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a vertical power FET configured to switch a load current and provide a channel of a first conductivity type; and a lateral FET configured to drive the vertical power FET and provide a channel of a second conductivity type opposing the first conductivity type; wherein the vertical power FET and the lateral FET are monolithically integrated into a semiconductor substrate of the first conductivity type, wherein a drain of the lateral FET is electrically coupled to a gate of the vertical power FET.

2 . The semiconductor device of claim 1 , wherein the semiconductor substrate comprises a first surface and a well of the second conductivity type extending into the semiconductor substrate from the first surface, wherein the lateral FET is formed in the well and comprises a plurality of trenches, each comprising a base and side walls, wherein a gate insulating layer is arranged at the base of the trenches and a gate electrode is arranged on the gate insulating layer.

3 . The semiconductor device of claim 2 , wherein a source region and a drain region of the lateral FET are arranged at the first surface, and wherein the base of the trenches is arranged in the semiconductor substrate.

4 . The semiconductor device of claim 2 , further comprising an electrically conductive dummy field plate that is arranged in the trenches above and electrically insulated from the gate electrode.

5 . The semiconductor device of claim 2 , wherein the vertical power FET comprises a plurality of trenches extending into the semiconductor substrate from the first surface, wherein each trench of the vertical power FET comprises a field plate arranged at a bottom of the trench and a gate electrode arranged above and electrically insulated from the field plate.

6 . The semiconductor device of claim 5 , wherein each trench of the vertical power FET is lined with an insulating layer that has a thickness on the base of the trench that is greater than a thickness of the gate insulating layer arranged on the base of the trenches of the lateral FET.

7 . The semiconductor device of claim 5 , wherein the plurality of trenches of the lateral FET and the plurality of trenches of the vertical power FET have substantially the same depth and substantially the same width.

8 . The semiconductor device of claim 2 , wherein the semiconductor substrate comprises a vertical drift region of the vertical power FET and a body region of the lateral FET, wherein the vertical power FET further comprises a body region arranged on the drift region, a source region at the first surface that is arranged on the body region, and a drain region arranged at a second surface of the semiconductor substrate that opposes the first surface, wherein the well forms a pn junction with the semiconductor substrate that is arranged at a greater depth from the first surface than a pn junction formed between the body region and the drift region of the vertical power FET.

9 . The semiconductor device of claim 1 , further comprising a further FET configured to drive the vertical power FET and provide a channel of the first conductivity type, wherein the further FET is monolithically integrated into the semiconductor substrate and has a drain coupled to the gate of the vertical power FET, and wherein the lateral FET and the further FET provide an output stage of a gate driver circuit.

10 . A method for fabricating a semiconductor device having a vertical power FET for switching a load current and a lateral FET for driving the vertical power FET, the method comprising:
forming a plurality of trenches in a first surface of a semiconductor substrate having a first conductivity type, each trench having a base and side walls; forming a first insulating layer that lines the base and the side walls of the trenches; in a first subset of the plurality of trenches that are located in a pre-defined area of the semiconductor substrate for forming a lateral FET comprising a channel region of a second conductivity type opposing the first conductivity type, removing the first insulating layer from the base of the first subset of trenches and forming a gate insulating layer on the base of the first subset of trenches; inserting conductive material into the plurality of trenches; removing the conductive material from an upper portion of the plurality of trenches and forming a gate electrode in the first subset of trenches and a field plate in a second subset of the plurality of trenches for forming the vertical power FET comprising a channel region of the first conductivity type, wherein the second subset of trenches is arranged outside of the pre-defined area and in a switching area of the semiconductor substrate.

11 . The method of claim 10 , further comprising:
forming a second insulating layer in the plurality of trenches that lines the side walls in the upper portion of the plurality of trenches that forms a gate insulating layer in the second subset of trenches; forming conductive material in at least the second subset of trenches and forming a gate electrode above and electrically insulated from the field plate; implanting dopants of the second conductivity type into the semiconductor substrate in the pre-defined area and forming a well having the second conductivity type; implanting dopants of the second conductivity type into the switching area to form a body region of the vertical power FET and implanting dopants of the first conductivity type into the switching area to form a source region on the body region; forming a third insulating layer on the first surface of the semiconductor substrate; in the switching area, forming an opening in the third insulating layer for a contact to each of the gate electrodes in the second subset of trenches and for a contact to each of the source regions; in the pre-defined area, forming an opening in the third insulating layer for a contact to the gate electrode in the first subset of trenches and to the well in the semiconductor substrate on opposing sides of individual ones of the first subset of trenches to form a source and drain contact for the lateral FET, respectively; and inserting conductive material into the openings.

12 . The method of claim 10 , wherein removing the first insulating layer from the base of the first subset of trenches and forming a gate insulating layer on the base of the first subset of trenches comprises:
covering the second subset of trenches in the switching area with a first mask; dry etching and reducing the thickness of the first insulating layer at the base of the first subset of trenches; wet etching the first insulating layer and removing the first insulating layer entirely from a portion of the base of the first subset of trenches and reducing the thickness of the first insulating layer on the side walls of the first subset of trenches; forming the gate insulating layer at the base of the first subset of trenches; and removing the first mask.

13 . The method of claim 12 , further comprising;
implanting dopants of the first conductivity type into the semiconductor substrate under the base of the first subset of trenches; and afterwards, forming the gate insulating layer on the base of the first subset of trenches.

14 . The method of claim 11 , further comprising:
covering the switching area with a second mask and then implanting the dopants of the second conductivity type into the semiconductor substrate in the pre-defined area to form the well; removing the second mask; and covering the pre-defined area with a third mask and then implanting the do

Assignees

• Infineon Technologies Austria Ag

Inventors

• Naik Harsh
• Henson Timothy
• Mirchandani Ashita
• Haase Robert
• He Honghai

Classifications

• H10P30/21

  of electrically active species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title