Data storage node voltage monitor circuit and methods for forming the same

Patent metadata

Field	Value
Publication number	US-12550318-B2
Application number	US-202318296389-A
Country	US
Kind code	B2
Filing date	Apr 6, 2023
Priority date	Apr 6, 2023
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A semiconductor device includes: an array of memory cells located over a substrate, wherein each of the memory cells includes a respective instance of an access transistor and a respective instance of a memory structure configured to store a data bit and electrically connected to a source structure of the respective instance of the access transistor; and a memory monitor device including an additional instance of the access transistor, an additional instance of the memory structure that is electrically connected to a source structure of the additional instance of the access transistor, and at least one monitor transistor having a respective monitor gate electrode that is electrically connected to the source structure of the additional instance of the access transistor.

First claim

What is claimed is:

1 . A semiconductor device comprising:
an array of memory cells located over a substrate, wherein each of the memory cells comprises a respective instance of an access transistor and a respective instance of a memory structure configured to store a data bit and electrically connected to a source structure of the respective instance of the access transistor; and a memory monitor device comprising an additional instance of the access transistor, an additional instance of the memory structure that is electrically connected to a source structure of the additional instance of the access transistor, and at least one monitor transistor having a respective monitor gate electrode that is electrically connected to the source structure of the additional instance of the access transistor.

2 . The semiconductor device of claim 1 , wherein a monitor gate electrode of the at least one monitor transistor is electrically connected to the source structure of the additional instance of the access transistor through at least one metal via structure and at least one metal line.

3 . The semiconductor device of claim 1 , wherein a monitor gate electrode of the at least one monitor transistor is in contact with the source structure of the additional instance of the access transistor.

4 . The semiconductor device of claim 1 , wherein:
each instance of the memory structure comprises a first electrode, a memory material layer or a node dielectric layer, and a second electrode; and the first electrode of the additional instance of the memory structure is electrically connected to the source structure of the additional instance of the access transistor through a metal via structure.

5 . The semiconductor device of claim 1 , wherein:
the substrate comprises a semiconductor material layer; and each instance of the access transistor comprises a respective single crystalline semiconductor channel.

6 . The semiconductor device of claim 1 , wherein each instance of the access transistor comprises a respective polycrystalline semiconducting metal oxide channel.

7 . The semiconductor device of claim 1 , wherein the at least one monitor transistor comprises a plurality of monitor transistors having different threshold voltages.

8 . The semiconductor device of claim 1 , wherein each instance of the memory structure comprises a respective capacitor structure including:
a respective first electrode that is electrically connected to the source structure of a respective instance of the access transistor; a respective node dielectric layer; and a respective second electrode.

9 . The semiconductor device of claim 1 , wherein each instance of the memory structure comprises:
a respective first electrode that is electrically connected to the source structure of a respective instance of the access transistor; a memory material portion having at least two resistivity states exhibiting different electrical resistivities; and a respective second electrode.

10 . A non-transitory machine-readable data storage medium that is encoded with a set of data representing a semiconductor circuit design, the set of data comprising:
a first data representing an array of memory cells located over a substrate, wherein each of the memory cells comprises a respective instance of an access transistor and a respective instance of a memory structure configured to store a data bit and electrically connected to a source structure of the respective instance of the access transistor; and a second data representing a memory monitor device comprising an additional instance of the access transistor, an additional instance of the memory structure that is electrically connected to a source structure of the additional instance of the access transistor, and at least one monitor transistor having a respective monitor gate electrode that is electrically connected to the source structure of the additional instance of the access transistor.

11 . The non-transitory machine-readable data storage medium of claim 10 , wherein a monitor gate electrode of the at least one monitor transistor is electrically connected to the source structure of the additional instance of the access transistor through at least one metal via structure and at least one metal line.

12 . The non-transitory machine-readable data storage medium of claim 10 , wherein a monitor gate electrode of the at least one monitor transistor is in contact with the source structure of the additional instance of the access transistor.

13 . The non-transitory machine-readable data storage medium of claim 10 , wherein:
each instance of the memory structure comprises a first electrode, a memory material layer or a node dielectric layer, and a second electrode; and the first electrode of the additional instance of the memory structure is electrically connected to the source structure of the additional instance of the access transistor through a metal via structure.

14 . The non-transitory machine-readable data storage medium of claim 10 , wherein the at least one monitor transistor comprises a plurality of monitor transistors having different threshold voltages.

15 . The non-transitory machine-readable data storage medium of claim 10 , wherein each instance of the memory structure comprises a respective capacitor structure including:
a respective first electrode that is electrically connected to the source structure of a respective instance of the access transistor; a respective node dielectric layer; and a respective second electrode.

16 . A method of forming a semiconductor device, the method comprising:
forming instances of an access transistor over a substrate; forming at least one monitor transistor having a respective monitor gate electrode; forming instances of a memory structure configured to store a respective data bit therein; and forming electrical connections to and from the instances of the access transistor, the at least one monitor transistor, and the instances of the memory structure, whereby an array of memory cells and a memory monitor device are formed, wherein:
each of the memory cells comprises a respective instance of the access transistor and a respective instance of the memory structure which is electrically connected to a source structure of the respective instance of the access transistor; and
the memory monitor device comprises an additional instance of the access transistor, an additional instance of the memory structure which is electrically connected to a source structure of the additional instance of the access transistor, and the at least one monitor transistor of which the respective monitor gate electrode is electrically connected to the source structure of the additional instance of the access transistor.

17 . The method of claim 16 , wherein a monitor gate electrode of the at least one monitor transistor is electrically connected to the source structure of the additional instance of the access transistor by forming at least one metal via structure and at least one metal line between the monitor gate electrode and the source structure.

18 . The method of claim 16 , wherein the source structure of the additional instance of the access transistor is formed directly on a monitor gate electrode of the at least one monitor transistor.

19 . The method of claim 16 , further comprising forming a metal via structure over the source structure of the additional instance of the access transistor, wherein:
each instance of the memory structure comprises a first e

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kao Yun-Feng
• Lee Wei
• Kuo Jyun-Yan
• Chiang Katherine H

Classifications

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C7/062

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title

• H10B12/09 Primary

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title

• H10B12/50 Primary

  Peripheral circuit region structures · CPC title