Optimizing central processing unit (CPU) cache memory DC power with rail voting scheme

Patent metadata

Field	Value
Publication number	US-12549182-B2
Application number	US-202418738893-A
Country	US
Kind code	B2
Filing date	Jun 10, 2024
Priority date	Jun 10, 2024
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

Aspects of the disclosure are directed to dc power consumption optimization in an extended reality (XR) device with thermal constraints. In accordance with one aspect, the disclosure includes performing a two-input logical AND operation using a first comparison state and a second comparison state as inputs to generate a first conjunctive output; performing a three-input logical AND operation using a third comparison state, a fourth comparison state and a fifth comparison state as inputs to generate a second conjunctive output; performing a two-input logical OR operation using the first conjunctive output and the second conjunctive output to generate a disjunctive output; and setting the disjunctive output to a select line for a two-input multiplexer to select either a processor voltage or a memory voltage as a voltage rail for an electrical load.

First claim

What is claimed is:

1 . An apparatus comprising:
a two-input AND logical function configured to perform a two-input logical AND operation using a first comparison state and a second comparison state as inputs to generate a first conjunctive output; a three-input AND logical function configured to perform a three-input logical AND operation using a third comparison state, a fourth comparison state and a fifth comparison state as inputs to generate a second conjunctive output; a two-input OR logical function coupled to the two-input AND logical function and the three-input AND logical function, the two-input OR logical function configured to perform a two-input logical OR operation using the first conjunctive output and the second conjunctive output to generate a disjunctive output; and a multiplexer coupled to two-input OR logical function, the multiplexer configured to select either a processor voltage or a memory voltage as a voltage rail for an electrical load.

2 . The apparatus of claim 1 , wherein the two-input AND logical function is further configured to receive a first comparison of the processor voltage and the memory voltage.

3 . The apparatus of claim 2 , wherein the two-input AND logical function is further configured to receive a second comparison of the processor voltage and a voltage threshold level.

4 . The apparatus of claim 3 , wherein the two-input AND logical function is further configured to receive the first comparison state and the second comparison state.

5 . The apparatus of claim 4 , wherein the two-input AND logical function is further configured to set the disjunctive output to a select line for a two-input multiplexer to select either the processor voltage or the memory voltage as the voltage rail for the electrical load.

6 . A method comprising:
performing a two-input logical AND operation using a first comparison state and a second comparison state as inputs to generate a first conjunctive output; performing a three-input logical AND operation using a third comparison state, a fourth comparison state and a fifth comparison state as inputs to generate a second conjunctive output; performing a two-input logical OR operation using the first conjunctive output and the second conjunctive output to generate a disjunctive output; and setting the disjunctive output to a select line for a two-input multiplexer to select either a processor voltage or a memory voltage as a voltage rail for an electrical load.

7 . The method of claim 6 , further comprising comparing the processor voltage to the memory voltage to generate the first comparison state.

8 . The method of claim 7 , further comprising comparing the processor voltage to a voltage threshold level to generate the second comparison state.

9 . The method of claim 8 , further comprising setting the first conjunctive output to TRUE if the first comparison state and the second comparison state are both TRUE; or setting the first conjunctive output to FALSE if either or both of the first comparison state and the second comparison state is FALSE.

10 . The method of claim 8 , further comprising comparing the memory voltage to the processor voltage to generate the third comparison state.

11 . The method of claim 10 , further comprising comparing the processor voltage to a minimum processor voltage to generate the fourth comparison state.

12 . The method of claim 11 , further comprising comparing the memory voltage to a minimum memory voltage to generate the fifth comparison state.

13 . The method of claim 12 , further comprising setting the second conjunctive output to TRUE if the third comparison state, the fourth comparison state and the fifth comparison state are all TRUE, or setting the second conjunctive output to FALSE if any of the third comparison state, the fourth comparison state or the fifth comparison state is FALSE.

14 . The method of claim 12 , further comprising determining the voltage threshold level.

15 . The method of claim 12 , further comprising setting the disjunctive output to TRUE if at least one of the first conjunctive output and the second conjunctive output is TRUE, or setting the disjunctive output to FALSE if both of the first conjunctive output and the second conjunctive output are FALSE.

16 . The method of claim 12 , further comprising selecting the processor voltage as the voltage rail for the electrical load if the disjunctive output is TRUE, or selecting the memory voltage as the voltage rail for the electrical load if the disjunctive output is FALSE.

17 . An apparatus comprising:
means for performing a two-input logical AND operation using a first comparison state and a second comparison state as inputs to generate a first conjunctive output; means for performing a three-input logical AND operation using a third comparison state, a fourth comparison state and a fifth comparison state as inputs to generate a second conjunctive output; means for performing a two-input logical OR operation using the first conjunctive output and the second conjunctive output to generate a disjunctive output; and means for setting the disjunctive output to a select line for a two-input multiplexer to select either a processor voltage or a memory voltage as a voltage rail for an electrical load.

18 . The apparatus of claim 17 , further comprising means for selecting the processor voltage as the voltage rail for the electrical load if the disjunctive output is TRUE, or for selecting the memory voltage as the voltage rail for the electrical load if the disjunctive output is FALSE.

19 . The apparatus of claim 18 , further comprising means for setting the second conjunctive output to TRUE if the third comparison state, the fourth comparison state and the fifth comparison state are all TRUE, or for setting the second conjunctive output to FALSE if any of the third comparison state, the fourth comparison state or the fifth comparison state is FALSE.

20 . The apparatus of claim 19 , further comprising means for setting the disjunctive output to TRUE if at least one of the first conjunctive output and the second conjunctive output is TRUE, or for setting the disjunctive output to FALSE if both of the first conjunctive output and the second conjunctive output are FALSE.

Assignees

• Qualcomm Inc

Inventors

• Garikipati Sreeharipriya
• Pande Pragya
• Mehrotra Ankur
• Singh Rohit

Classifications

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K19/0008 Primary

  Arrangements for reducing power consumption · CPC title