Voltage ramp generator

Patent metadata

Field	Value
Publication number	US-12549162-B2
Application number	US-202418798124-A
Country	US
Kind code	B2
Filing date	Aug 8, 2024
Priority date	Aug 9, 2023
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A circuit includes a first capacitance array formed by n nominally equal capacitive elements. A first electrode of each capacitive element is coupled, via respective switches to either a reference voltage or ground. A differential amplifier has a first input coupled to an output of a first capacitance array, a second input grounded, and an output generating a voltage ramp. A capacitive feedback circuit couples the output of the differential amplifier to the first input. A second capacitance array has an output coupled to the first input of the differential amplifier. The capacitive elements of the first capacitance array are organized in sets. The circuit operates by controllably coupling, set by set, second electrodes of the capacitive elements of the first capacitance array to the first input of the differential amplifier.

First claim

The invention claimed is:

1 . A circuit, comprising:
a first capacitance array comprising n nominally equal input capacitive elements each having a first electrode coupled, via respective switches, to one of a reference voltage or ground; a differential amplifier having a first input coupled to an output of the first capacitance array, a second input coupled to ground, and an output providing a voltage ramp; and a capacitive feedback circuit coupling the output of said differential amplifier to the first input of the differential amplifier; and a second capacitance array having an output coupled to the first input of the differential amplifier; wherein the input capacitive elements are organized in sets and second electrodes of the input capacitive elements are interconnected, set by set, and controllably couplable to the first input of the differential amplifier.

2 . The circuit of claim 1 , wherein the input capacitive elements are organized in m sets of n/(2 j ) capacitive elements, j ranging from 1 to m, plus one set of n/(2 m ) capacitive elements, where 2 m represents a maximum conversion gain.

3 . The circuit of claim 2 , wherein a conversion gain conditions the number of sets coupled to the first input of amplifier.

4 . The circuit of claim 3 , wherein the second capacitance array provides steps having an amplitude corresponding to a main digital to analog converter (DAC), divided by the conversion gain.

5 . The circuit claim 3 , wherein the sets of input capacitive elements of the first capacitance array are in parallel, m switches coupling individually each of the m first sets to the first input of the differential amplifier and said one set of n/(2 m ) capacitive elements is permanently connected to said first input.

6 . The circuit of claim 5 , wherein each of the m first sets of capacitive elements of the first capacitance array is coupled to the set of capacitive elements of higher rank j by a switch and said one set of n/(2 m ) capacitive elements is permanently connected to said first input.

7 . The circuit of claim 3 , wherein a frequency of output steps in the voltage ramp remains the same for all conversion gains.

8 . The circuit of claim 1 , wherein a switching of the input capacitive elements is made at a given frequency to define voltage steps in the output signal of the differential amplifier, a duration of steps of the first capacitance array corresponding to a duration of steps of the second capacitance array multiplied by a conversion gain.

9 . The circuit of claim 8 , wherein the conversion gain conditions a number of sets of input capacitive elements which are coupled to the first input of the differential amplifier.

10 . The circuit of claim 8 , wherein the second capacitance array provides steps having an amplitude corresponding to a main digital to analog converter (DAC), divided by the conversion gain.

11 . The circuit of claim 8 , wherein a frequency of output steps in the voltage ramp remains the same for all conversion gains.

12 . The circuit of claim 1 , wherein the input capacitive elements are organized in sets and further comprising control circuitry configured to controllably couple, set by set, second electrodes of the input capacitive elements to said first input of the amplifier.

13 . A voltage ramp generator comprising the circuit according to claim 1 .

14 . A digital-to-analog converter comprising the voltage ramp generator according to claim 13 .

15 . An image sensor comprising at least one digital-to-analog converter according to claim 14 .

Assignees

• St Microelectronics Int Nv

Inventors

• Mekki Abdessamed
• Simony Laurent

Classifications

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H03K4/023 Primary

  by repetitive charge or discharge of a capacitor, analogue generators · CPC title

• H03M1/56 Primary

  Input signal compared with linear ramp · CPC title