Memory system having a non-volatile memory and a controller configured to switch a mode for controlling an access operation to the non-volatile memory

Patent metadata

Field	Value
Publication number	US-12548624-B2
Application number	US-202318455575-A
Country	US
Kind code	B2
Filing date	Aug 24, 2023
Priority date	Mar 18, 2020
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.

First claim

What is claimed is:

1 . A solid state drive comprising:
a non-volatile memory; and a controller configured to select one of a plurality of modes for controlling a write operation to the non-volatile memory, based on a first parameter received from a host, wherein the plurality of modes includes at least a first mode, a second mode, and a third mode, a length of a lifetime of data written to the non-volatile memory in the first mode is shorter than a length of a lifetime of data written to the non-volatile memory in the third mode, and the length of the lifetime of data written to the non-volatile memory in the third mode is shorter than a length of a lifetime of data written to the non-volatile memory in the second mode.

2 . The solid state drive according to claim 1 , wherein the first parameter includes a hint of a lifetime of data.

3 . The solid state drive according to claim 1 , wherein the first parameter is included in a command provided from the host.

4 . The solid state drive according to claim 1 , wherein
the controlling of the write operation according to the first mode includes setting a size of increase in a program voltage during a programming loop executed in the non-volatile memory, to a first voltage increase size, the controlling of the write operation according to the third mode includes setting the size of increase in the program voltage during the programming loop executed in the non-volatile memory, to a third voltage increase size that is smaller than the first voltage increase size, and the controlling of the write operation according to the second mode includes setting the size of increase in the program voltage during the programming loop executed in the non-volatile memory, to a second voltage increase size that is smaller than the third voltage increase size.

5 . The solid state drive according to claim 1 , wherein
the non-volatile memory includes a plurality of memory cells, the controlling of the write operation according to the third mode includes controlling the non-volatile memory to store a third number of bits per memory cell, and the controlling of the write operation according to the second mode includes controlling the non-volatile memory to store a second number of bits per memory cell, the second number being smaller than the third number.

6 . The solid state drive according to claim 1 , wherein
a user capacity of the non-volatile memory when the non-volatile memory is controlled according to the second mode is smaller than the user capacity of the non-volatile memory when the non-volatile memory is controlled according to the third mode.

7 . The solid state drive according to claim 1 , wherein
the controlling of the write operation according to the third mode includes setting the read pass voltage to be applied to the non-selected word lines during the write verification operation to a third voltage, and the controlling of the write operation according to the second mode includes setting the read pass voltage to be applied to the non-selected word lines during the write verification operation to a second voltage that is higher than the third voltage.

8 . A method of controlling a non-volatile memory, the method comprising:
receiving a first parameter received from a host; and selecting one of a plurality of modes for controlling a write operation to the non-volatile memory, based on the first parameter received from the host, wherein the plurality of modes includes at least a first mode, a second mode, and a third mode, a length of a lifetime of data written to the non-volatile memory in the first mode is shorter than a length of a lifetime of data written to the non-volatile memory in the third mode, and the length of the lifetime of data written to the non-volatile memory in the third mode is shorter than a length of a lifetime of data written to the non-volatile memory in the second mode.

9 . The method according to claim 8 , wherein the first parameter includes a hint of a lifetime of data.

10 . The method according to claim 8 , wherein the first parameter is included in a command provided from the host.

11 . The method according to claim 8 , wherein
the controlling of the write operation according to the first mode includes setting a size of increase in a program voltage during a programming loop executed in the non-volatile memory, to a first voltage increase size, the controlling of the write operation according to the third mode includes setting the size of increase in the program voltage during the programming loop executed in the non-volatile memory, to a third voltage increase size that is smaller than the first voltage increase size, and the controlling of the write operation according to the second mode includes setting the size of increase in the program voltage during the programming loop executed in the non-volatile memory, to a second voltage increase size that is smaller than the third voltage increase size.

12 . The method according to claim 8 , wherein
the non-volatile memory includes a plurality of memory cells, the controlling of the write operation according to the third mode includes controlling the non-volatile memory to store a third number of bits per memory cell, and the controlling of the write operation according to the second mode includes controlling the non-volatile memory to store a second number of bits per memory cell, the second number being smaller than the third number.

13 . The method according to claim 8 , wherein
a user capacity of the non-volatile memory when the non-volatile memory is controlled according to the second mode is smaller than the user capacity of the non-volatile memory when the non-volatile memory is controlled according to the third mode.

14 . The method according to claim 8 , wherein
the controlling of the write operation according to the third mode includes setting the read pass voltage to be applied to the non-selected word lines during the write verification operation to a third voltage, and the controlling of the write operation according to the second mode includes setting the read pass voltage to be applied to the non-selected word lines during the write verification operation to a second voltage that is higher than the third voltage.

15 . A method of controlling a non-volatile memory, the non-volatile memory including a plurality of memory cells, the method comprising:
receiving a first parameter received from a host; and selecting one of a plurality of modes for controlling a write operation to the non-volatile memory, based on the first parameter received from the host, wherein the plurality of modes includes at least a first mode and a second mode; and a length of a lifetime of data written to the non-volatile memory in the first mode is different from a length of a lifetime of data written to the non-volatile memory in the second mode.

16 . The method according to claim 15 , wherein the first parameter includes a hint of a lifetime of data.

17 . The method according to claim 15 , wherein the first parameter is included in a command provided from the host.

18 . The method according to claim 15 , wherein the length of the lifetime of data written to the non-volatile memory in the second mode is longer than the length of the lifetime of data written to the non-volatile memory in the first mode.

19 . The method according to claim 18 , wherein
the controlling of the write operation according to the first mode includes setting a size of increase in a

Assignees

• Kioxia Corp

Inventors

• Suzuki Riki
• Kojima Yoshihisa

Classifications

• G11C16/30

  Power supply circuits · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title

• G11C16/22

  Safety or protection circuits preventing unauthorised or accidental access to memory cells · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title