Display device

Patent metadata

Field	Value
Publication number	US-12548501-B2
Application number	US-202519022342-A
Country	US
Kind code	B2
Filing date	Jan 15, 2025
Priority date	Apr 11, 2024
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A display device includes a data line, and first, second, and third pixels electrically connected to the data line. Each of the first, second, and third pixels includes a light emitting element, a first transistor that controls a control current, a second transistor that electrically connects the data line to a second node, which is a first electrode of the first transistor, a third transistor that electrically connects the first node to a third node, which is a second electrode of the first transistor, a fourth transistor that controls a driving current, which is supplied to the light emitting element, and a fifth transistor that electrically connects the data line to a fifth node, which is a first electrode of the fourth transistor. The data line is electrically connected to the fifth transistor of each of the first and second pixels through a connection electrode.

First claim

What is claimed is:

1 . A display device comprising:
a data line extending in a first direction; and a first pixel, a second pixel, and a third pixel sequentially disposed in the first direction and electrically connected to the data line, wherein each of the first, second, and third pixels comprises:
a light emitting element;
a first transistor that controls a control current based on a voltage of a first node;
a second transistor that electrically connects the data line to a second node, which is a first electrode of the first transistor based on a first scan write signal;
a third transistor that electrically connects the first node to a third node, which is a second electrode of the first transistor, based on the first scan write signal;
a fourth transistor that controls a driving current, which is supplied to the light emitting element, based on a voltage of a fourth node receiving the control current;
a fifth transistor that electrically connects the data line to a fifth node, which is a first electrode of the fourth transistor, based on a second scan write signal; and
a sixth transistor that electrically connects the fourth node to a sixth node, which is a second electrode of the fourth transistor, based on the second scan write signal, and the data line is electrically connected to the fifth transistor of each of the first and second pixels through a connection electrode.

2 . The display device of claim 1 , wherein the connection electrode overlaps a boundary area of the first and second pixels.

3 . The display device of claim 1 , wherein the data line comprises:
a plurality of first portions electrically connected to the second transistors of the first and second pixels, respectively; and a second portion simultaneously connected to the fifth transistors of the first and second pixels.

4 . The display device of claim 3 , wherein
one of the first portions of the data line supplies a first data voltage having a grayscale value of the first pixel in case that the second and third transistors of the first pixel are turned on, another one of the first portions of the data line supplies a first data voltage having a grayscale value of the second pixel in case that the second and third transistors of the second pixel are turned on, and the second portion of the data line supplies a second data voltage, which is a constant voltage, in case that the fifth and sixth transistors of the first and second pixels are turned on.

5 . The display device of claim 1 , further comprising:
a sweep line supplying a sweep signal having a pulse that linearly decreases from a gate-high voltage to a gate-low voltage; and a first capacitor comprising a first capacitor electrode connected to the first node and a second capacitor electrode connected to the sweep line.

6 . The display device of claim 1 , wherein
the first and fourth transistors comprise a low-temperature polysilicon-based semiconductor layer, and the second, third, fifth and sixth transistors comprise an oxide-based semiconductor layer.

7 . The display device of claim 1 , further comprising:
an emission line extending in a second direction intersecting the first direction, wherein each of the first, second, and third pixels further comprises:
a seventh transistor that supplies a first high-potential voltage to the second node based on an emission signal of the emission line; and
an eighth transistor that electrically connects the third node to the fourth node based on the emission signal.

8 . The display device of claim 7 , wherein
the seventh transistor of the second pixel and the seventh transistor of the third pixel are electrically connected to an emission line.

9 . The display device of claim 7 , wherein
the emission line overlaps a boundary area of the second and third pixels.

10 . The display device of claim 7 , wherein
each of the first, second, and third pixels further comprises:
a ninth transistor that supplies a second high-potential voltage to the fifth node based on the emission signal; and
a tenth transistor that electrically connects the sixth node to a seventh node, which is a first electrode of the light emitting element, based on the emission signal.

11 . The display device of claim 10 , wherein
each of the first, second, and third pixels further comprises:
an eleventh transistor that discharges the first node to an initialization voltage based on a first scan initialization signal; and
a twelfth transistor that discharges the fourth node to the initialization voltage based on a second scan initialization signal.

12 . The display device of claim 11 , further comprising:
a first low-potential line that supplies a first low-potential voltage to a second electrode of the light emitting element, wherein each of the first, second, and third pixels further comprises a thirteenth transistor discharging the seventh node to a second low-potential voltage based on the voltage of the fourth node.

13 . A display device comprising:
a data line extending in a first direction; an emission line extending in a second direction intersecting the first direction; and a first pixel, a second pixel, and a third pixel sequentially disposed in the first direction and electrically connected to the data line, wherein each of the first, second, and third pixels comprises:
a light emitting element;
a first transistor that controls a control current based on a voltage of a first node;
a second transistor that is turned on during a first period to electrically connect the data line to a second node, which is a first electrode of the first transistor;
a third transistor that is turned on during the first period to electrically connect the first node to a third node, which is a second electrode of the first transistor;
a fourth transistor that supplies a first high-potential voltage to the second node based on an emission signal of the emission line; and
a fifth transistor that electrically connects the third node to a fourth node based on the emission signal,
the fourth transistor of the second pixel and the fourth transistor of the third pixel are electrically connected to an emission line.

14 . The display device of claim 13 , wherein the emission line overlaps a boundary area of the second and third pixels.

15 . The display device of claim 13 , wherein
the emission line comprises:
an extending portion extending in the second direction;
a first protruding portion protruding from the extending portion toward a first side and overlapping the second pixel; and
a second protruding portion protruding from the extending portion toward a second side opposite to the first side and overlapping the third pixel.

16 . The display device of claim 15 , wherein
the first protruding portion of the emission line comprises a gate electrode of the fourth transistor of the second pixel, and the second protruding portion comprises a gate electrode of the fourth transistor of the third pixel.

17 . The display device of claim 13 , wherein
each of the first, second, and third pixels further comprises:
a sixth transistor that discharges the first node to an initialization voltage during a second period before the first period;
a seventh transistor that controls a driving current, which is supplied to the light emitting element, based on a voltage of the fourth node receiving the control current;
an eighth transistor that is turned on during a third period after the first period to electrically connect the data line to a fifth node, which is

Assignees

• Samsung Display Co Ltd

Inventors

• Shin Dong Hee
• Son Sun Kwun
• Cha Na Hyeon

Classifications

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G3/2007

  Display of intermediate tones · CPC title

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title