Shift register and driving method therefor, gate driving circuit, and display device

Patent metadata

Field	Value
Publication number	US-12548487-B2
Application number	US-202519023209-A
Country	US
Kind code	B2
Filing date	Jan 15, 2025
Priority date	Sep 28, 2021
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A shift register and a driving method therefor, a gate driving circuit and a display device are provided, wherein the shift register includes a pull-up control sub-circuit configured to provide a signal of a first signal terminal or a second signal terminal to a pull-up control node under control of a first input terminal and a second output terminal; the pull-down control sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, a first clock signal terminal and a second clock signal terminal; the output sub-circuit is configured to supply a signal of a third clock signal terminal to a first output terminal and a signal of a fourth clock signal terminal to the second output terminal.

First claim

The invention claimed is:

1 . A shift register, comprising a pull-up control sub-circuit, a pull-down control sub-circuit, an output sub-circuit and a noise reduction sub-circuit;
wherein the pull-up control sub-circuit is electrically connected with a first input terminal, a second output terminal, a first signal terminal, a second signal terminal and a pull-up control node, respectively, and is configured to provide a signal of the first signal terminal or the second signal terminal to the pull-up control node under control of the first input terminal and the second output terminal; the pull-down control sub-circuit is electrically connected with a first clock signal terminal, a second clock signal terminal, the first signal terminal, the second signal terminal, the pull-up control node, a pull-down node, a first power supply terminal and a second power supply terminal, respectively, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, the first clock signal terminal and the second clock signal terminal; the output sub-circuit comprises a first output sub-circuit and a second output sub-circuit; the output sub-circuit is electrically connected with the pull-up control node, the first power supply terminal, a third clock signal terminal, a first output terminal, a fourth clock signal terminal and the second output terminal, respectively, and is configured to provide a signal of the third clock signal terminal to the first output terminal and provide a signal of the fourth clock signal terminal to the second output terminal under control of the pull-up control node and the first power supply terminal; and the noise reduction sub-circuit is electrically connected with the pull-up control node, the first output terminal, the second output terminal, the pull-down node and the second power supply terminal, respectively, and is configured to provide a signal of the second power supply terminal to the pull-up control node, the first output terminal and the second output terminal under control of the pull-down node; wherein the pull-up control sub-circuit comprises a first transistor and a second transistor, the pull-down control sub-circuit comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a first capacitor, the first output sub-circuit comprises a seventh transistor, an eighth transistor and a second capacitor, the second output sub-circuit comprises a ninth transistor, a tenth transistor and a third capacitor, and the noise reduction sub-circuit comprises an eleventh transistor, a twelfth transistor, and a thirteenth transistor; and a ratio of a capacitance value of the first capacitor to a capacitance value of the second capacitor or the third transistor is greater than 1 and less than 2.

2 . The shift register according to claim 1 , wherein a ratio of a length of the eighth transistor to a length of the twelfth transistor is greater than 3.

3 . The shift register according to claim 1 , wherein a ratio of a length of the sixth transistor to a length of the fifth transistor is greater than 4.

4 . The shift register according to claim 1 , wherein a ratio of a length of the seventh transistor to a length of the fourteenth transistor is greater than 1.8.

5 . The shift register according to claim 1 , wherein the first output sub-circuit is electrically connected with the pull-up control node, the first power supply terminal, the third clock signal terminal and the first output terminal, respectively, and is configured to provide the signal of the third clock signal terminal to the first output terminal under control of the first power supply terminal and the pull-up control node; and
the second output sub-circuit is electrically connected with the pull-up control node, the first power supply terminal, the fourth clock signal terminal and the second output terminal, respectively, and is configured to provide the signal of the fourth clock signal terminal to the second output terminal under control of the first power supply terminal and the pull-up control node.

6 . The shift register according to claim 1 , further comprising a reset sub-circuit;
wherein the reset sub-circuit is electrically connected with a reset signal terminal, the pull-up control node and the second power supply terminal, respectively, and is configured to provide a signal of the second power supply terminal to the pull-up control node under control of the reset signal terminal.

7 . The shift register according to claim 1 , wherein a control electrode of the first transistor is electrically connected with the first input terminal, a first electrode of the first transistor is electrically connected with the first signal terminal, and a second electrode of the first transistor is electrically connected with the pull-up control node; and
a control electrode of the second transistor is electrically connected with the second input terminal, a first electrode of the second transistor is electrically connected with the second signal terminal, and a second electrode of the second transistor is electrically connected with the pull-up control node.

8 . The shift register according to claim 1 , wherein a control electrode of the third transistor is electrically connected with the first signal terminal, a first electrode of the third transistor is electrically connected with the first clock signal terminal, and a second electrode of the third transistor is electrically connected with a pull-down control node;
a control electrode of the fourth transistor is electrically connected with the second signal terminal, a first electrode of the fourth transistor is electrically connected with the second clock signal terminal, and a second electrode of the fourth transistor is electrically connected with the pull-down control node; a control electrode of the fifth transistor is electrically connected with the pull-down control node, a first electrode of the fifth transistor is electrically connected with the first power supply terminal, and a second electrode of the fifth transistor is electrically connected with the pull-down node; a control electrode of the sixth transistor is electrically connected with the pull-up control node, a first electrode of the sixth transistor is electrically connected with the pull-down node, and a second electrode of the sixth transistor is electrically connected with the second power supply terminal; and a first electrode of the first capacitor is electrically connected with the pull-down node, and a second electrode of the first capacitor is electrically connected with the second power supply terminal.

9 . The shift register according to claim 1 , wherein a control electrode of the seventh transistor is electrically connected with the first power supply terminal, a first electrode of the seventh transistor is electrically connected with the pull-up control node, and a second electrode of the seventh transistor is electrically connected with a first pull-up node;
a control electrode of the eighth transistor is electrically connected with the first pull-up node, a first electrode of the eighth transistor is electrically connected with the third clock signal terminal, and a second electrode of the eighth transistor is electrically connected with the first output terminal; and a first electrode of the second capacitor is electrically connected with the first pull-up node, and a second electrode of the second capacitor is electrically connected with the first output terminal.

10 . The shift register according to

Assignees

• Boe Technology Group Co Ltd

Inventors

• Yan Wei
• Wang Zhen
• Qin Wenwen
• Zhang Han
• Wang Deshuai
• Zhang Jian
• Shan Yue
• Yang Xiaoyan
• Zhang Yadong
• Sun Jian

Classifications

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2300/08

  Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title