Device and method for neural network computing, and board and readable storage medium

Patent metadata

Field	Value
Publication number	US-12547902-B2
Application number	US-202118003682-A
Country	US
Kind code	B2
Filing date	Sep 23, 2021
Priority date	Sep 28, 2020
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

The present disclosure relates to an apparatus and a method for performing neural network computing, a board card, and a readable storage medium. The computing apparatus of the present disclosure is included in an integrated circuit apparatus. The integrated circuit apparatus includes a general interconnection interface and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The integrated circuit apparatus further includes a storage apparatus. The storage apparatus is connected to the computing apparatus and other processing apparatus, respectively. The storage apparatus is used for data storage of the computing apparatus and other processing apparatus.

First claim

What is claimed:

1 . An integrated circuit apparatus for performing neural network computing, comprising:
a processing apparatus configured to create a template fuse unit; a compiler configured to convert the template fuse unit into an object code; a linker configured to link the object code with a library to form an executable file; and a computing apparatus configured to perform the executable file to implement the neural network computing, wherein, when converting the template fuse unit into the object code, the compiler derives a shape of the template fuse unit, and wherein the compiler performs a reverse derivation forward from outputs for required input data and redundancy.

2 . The integrated circuit apparatus of claim 1 , wherein, when creating the template fuse unit, the processing apparatus is configured to:
select a starting layer of the template fuse unit according to a starting rule of a fusion policy; and perform a fusion based on the starting layer and check rules of the fusion policy to create the template fuse unit.

3 . The integrated circuit apparatus of claim 1 , wherein the compiler derives an address of on-chip storage space of a whole control flow graph and implements access to a general address.

4 . The integrated circuit apparatus of claim 3 , wherein the compiler is configured to:
divide basic blocks initially according to a division of the template fuse unit; and confirm the basic blocks and mutual relations between the basic blocks after iterative operations.

5 . The integrated circuit apparatus of claim 3 , wherein the compiler is configured to:
judge how much data in a previous template fuse unit is able to be used by a next template fuse unit; and plan the address of on-chip storage space according to a judging result.

6 . The integrated circuit apparatus of claim 5 , wherein the processing apparatus allocates on-chip storage space according to the address of on-chip storage space.

7 . A board card, comprising an integrated circuit apparatus that includes:
a processing apparatus configured to create a template fuse unit; a compiler configured to convert the template fuse unit into an object code; a linker configured to link the object code with a library to form an executable file; and
a computing apparatus configured to perform the executable file to implement the neural network computing,
wherein the compiler derives a shape of the template fuse unit in converting the template fuse unit into the object code, and
wherein the compiler performs a reverse derivation forward from outputs for required input data and redundancy.

8 . The board card of claim 7 , wherein the processing apparatus is further configured to:
select a starting layer of the template fuse unit according to a starting rule of a fusion policy; and perform a fusion based on the starting layer and check rules of the fusion policy to create the template fuse unit.

9 . The board card of claim 7 , wherein the compiler derives an address of on-chip storage space of a whole control flow graph and implements access to a general address.

10 . The board card of claim 9 , wherein the compiler is configured to:
divide basic blocks initially according to a division of the template fuse unit; and confirm the basic blocks and mutual relations between the basic blocks after iterative operations.

11 . The board card of claim 9 , wherein the compiler is configured to:
judge how much data in a previous template fuse unit is able to be used by a next template fuse unit; and plan the address of on-chip storage space according to a judging result.

12 . The board card of claim 11 , wherein the processing apparatus allocates on-chip storage space according to the address of on-chip storage space.

Assignees

• Cambricon Tech Corp Ltd

Inventors

• Lan Huiying
• Wang Ruitao
• Luo Haizhao
• Cao Bo
• Chen Xunyu

Classifications

• G06N3/048

  Activation functions · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/10 Primary

  Interfaces, programming languages or software development kits, e.g. for simulating neural networks · CPC title

• G06N3/063 Primary

  using electronic means · CPC title