Method and apparatus for checking signal line

Patent metadata

Field	Value
Publication number	US-12547812-B2
Application number	US-202217898727-A
Country	US
Kind code	B2
Filing date	Aug 30, 2022
Priority date	May 25, 2022
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

A method and an apparatus for checking a signal line are provided. The method includes: obtaining custom design information of a target signal line in a circuit schematic, and generating a layout design rule corresponding to the target signal line based on the custom design information; checking whether the target signal line meets the layout design rule in a circuit layout corresponding to the circuit schematic; and adding a first label to a position of the target signal line in the circuit layout when the target signal line in the circuit layout does not meet the layout design rule. The first label is configured to indicate that the target signal line does not meet the layout design rule.

First claim

What is claimed is:

1 . A method for checking a signal line in a circuit layout, comprising:
obtaining custom design information of a target signal line in a circuit schematic, and generating a layout design rule corresponding to the target signal line based on the custom design information; generating the circuit layout based on the circuit schematic, and adding a third label to a position of the target signal line in the circuit layout, wherein the third label comprises the custom design information corresponding to the target signal line obtained from the circuit schematic; checking whether the target signal line meets the layout design rule; and adding a first label to the position of the target signal line in the circuit layout in response to the target signal line in the circuit layout not meeting the layout design rule, wherein the first label is configured to indicate that the target signal line does not meet the layout design rule, wherein after adding the first label to the position of the target signal line in the circuit layout, the method further comprises: modifying the target signal line in the circuit layout based on the third label added to the position of the target signal line in the circuit layout until the target signal line in the circuit layout meets the layout design rule.

2 . The method of claim 1 , wherein before obtaining the custom design information of the target signal line in the circuit schematic, the method further comprises:
receiving the custom design information corresponding to the target signal line inputted by a user; and adding a second label to the target signal line in the circuit schematic, wherein the second label comprises the custom design information.

3 . The method of claim 1 , further comprising:
determining the position of the target signal line in the circuit layout based on a position of the target signal line in the circuit schematic by using a layout versus schematics (LVS) tool.

4 . The method of claim 1 , wherein the custom design information comprises at least one of a width of the target signal line, a surrounding environment, and a spacing for the target signal line.

5 . The method of claim 1 , wherein the target signal line comprises a sensitive signal line or a noise signal line.

6 . An apparatus for checking a signal line in a circuit layout, comprising at least one processor and a memory, wherein the memory stores computer executable instructions, and the at least one processor executes the computer executable instructions to:
obtain custom design information of a target signal line in a circuit schematic, and generate a layout design rule corresponding to the target signal line based on the custom design information; generate the circuit layout based on the circuit schematic, and add a third label to a position of the target signal line in the circuit layout, wherein the third label comprises the custom design information corresponding to the target signal line obtained from the circuit schematic; check whether the target signal line meets the layout design rule; add a first label to the position of the target signal line in the circuit layout in response to the target signal line in the circuit layout not meeting the layout design rule, wherein the first label is configured to indicate that the target signal line does not meet the layout design rule; and modify the target signal line in the circuit layout based on the third label added to the position of the target signal line in the circuit layout until the target signal line in the circuit layout meets the layout design rule.

7 . The apparatus of claim 6 , wherein the at least one processor executes the computer executable instructions to:
receive the custom design information corresponding to the target signal line inputted by a user; and add a second label to the target signal line in the circuit schematic, wherein the second label comprises the custom design information.

8 . The apparatus of claim 6 , wherein the at least one processor executes the computer executable instructions to:
determine the position of the target signal line in the circuit layout based on a position of the target signal line in the circuit schematic by using an LVS tool.

9 . The apparatus of claim 6 , wherein the custom design information comprises at least one of a width of the target signal line, a surrounding environment, and a spacing for the target signal line.

10 . The apparatus of claim 6 , wherein the target signal line comprises a sensitive signal line or a noise signal line.

11 . A non-transitory computer-readable storage medium configured with computer executable instructions, wherein upon being executed by one or more processors, the instructions cause the one or more processors to perform operations for checking a signal line in a circuit layout, the operations comprise:
obtaining custom design information of a target signal line in a circuit schematic, and generating a layout design rule corresponding to the target signal line based on the custom design information; generating the circuit layout based on the circuit schematic, and adding a third label to a position of the target signal line in the circuit layout, wherein the third label comprises the custom design information corresponding to the target signal line obtained from the circuit schematic; checking whether the target signal line meets the layout design rule; and adding a first label to the position of the target signal line in the circuit layout in response to the target signal line in the circuit layout not meeting the layout design rule, wherein the first label is configured to indicate that the target signal line does not meet the layout design rule, wherein after adding the first label to the position of the target signal line in the circuit layout, the operations performed by the one or more processors further comprises: modifying the target signal line in the circuit layout based on the third label added to the position of the target signal line in the circuit layout until the target signal line in the circuit layout meets the layout design rule.

12 . The non-transitory computer-readable storage medium of claim 11 , wherein before obtaining the custom design information of the target signal line in the circuit schematic, the operations performed by the one or more processors further comprises:
receiving the custom design information corresponding to the target signal line inputted by a user; and adding a second label to the target signal line in the circuit schematic, wherein the second label comprises the custom design information.

13 . The non-transitory computer-readable storage medium of claim 11 , wherein the operations performed by the one or more processors further comprises:
determining the position of the target signal line in the circuit layout based on a position of the target signal line in the circuit schematic by using a layout versus schematics (LVS) tool.

14 . The non-transitory computer-readable storage medium of claim 11 , wherein the custom design information comprises at least one of a width of the target signal line, a surrounding environment, and a spacing for the target signal line.

Assignees

• Changxin Memory Tech Inc

Inventors

• Min Min
• Jiang Wei
• Bai Li
• Chen Chuanjiang

Classifications

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title