Read operations for active regions of a memory device

Patent metadata

Field	Value
Publication number	US-12547328-B2
Application number	US-202418781613-A
Country	US
Kind code	B2
Filing date	Jul 23, 2024
Priority date	Mar 16, 2021
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

Methods, systems, and devices for read operations for active regions of a memory device are described. A memory system that includes a non-volatile memory device may receive a command to enter a first power mode. Before entering the first power mode, the memory system may store an indication of the active regions of the non-volatile memory device that are active for use as part of a host performance booster (HPB) mode. The memory device may receive an HPB command while in the first power mode, and may subsequently enter (e.g., re-enter) the second power mode. In some examples, the HPB command may be processed based on its physical address being included in one of the active regions of the non-volatile memory device.

First claim

What is claimed is:

1 . A memory system, comprising:
one or more non-volatile memory devices; one or more caches for storing mappings between logical addresses and physical addresses of the one or more non-volatile memory devices; and processing circuitry coupled with the one or more non-volatile memory devices and the one or more caches, wherein the processing circuitry is configured to cause the memory system to:
store an indication of an active region of the one or more non-volatile memory devices that is configured for use as part of a host performance booster mode;
enter a first power mode in accordance with storing the indication;
transition to a second power mode from the first power mode; and
perform, while the one or more non-volatile memory devices is operating in the second power mode, an access operation using a physical address of the one or more non-volatile memory devices.

2 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
receive an access command that includes the physical address of one or more memory cells the one or more non-volatile memory devices in the active region of the one or more non-volatile memory devices, wherein transitioning to the second power mode from the first power mode is in accordance with receiving the access command; and determine whether the physical address of the access command is associated with the active region, wherein performing the access operation is in accordance with determining that the physical address of the access command is associated with the active region.

3 . The memory system of claim 2 , wherein the indication of the active region of the one or more non-volatile memory devices comprises a starting address and a quantity of addresses in the active region associated with one or more physical addresses of the one or more non-volatile memory devices.

4 . The memory system of claim 3 , wherein the processing circuitry is further configured to cause the memory system to:
determine, in accordance with the indication stored in the one or more non-volatile memory devices, whether the physical address of the access command is associated with the active region in accordance with comparing the physical address associated with the access command with the starting address and the quantity of addresses associated with the active region, wherein performing the access operation is in accordance with determining that the physical address of the access command is associated with the active region.

5 . The memory system of claim 2 , wherein the indication of the active region of the one or more non-volatile memory devices comprises a bitmap associated with one or more physical addresses of the one or more non-volatile memory devices.

6 . The memory system of claim 5 , wherein the processing circuitry is further configured to cause the memory system to:
determine, in accordance with the indication stored in the one or more non-volatile memory devices, whether the physical address of the access command is associated with the active region in accordance with comparing at least one bit associated with the access command to the bitmap stored to the one or more caches, wherein performing the access operation is in accordance with determining that the physical address of the access command is associated with the active region.

7 . The memory system of claim 1 , wherein, to enter the first power mode, the processing circuitry is further configured to cause the memory system to:
enter the first power mode after failing to receive, from a host system, a command within a duration.

8 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
receive a command for entering the first power mode, wherein entering the first power mode is in response to receiving the command.

9 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
transmit, to a host system, a portion of the mappings between the logical addresses and the physical addresses of the one or more non-volatile memory devices, wherein storing the indication of the active region of the one or more non-volatile memory devices is in accordance with transmitting the portion of the mappings to the host system and wherein the active region of the one or more non-volatile memory devices correspond to the physical addresses of the one or more non-volatile memory devices included in the portion of the mappings transmitted to the host system.

10 . A memory system, comprising:
one or more non-volatile memory devices; one or more caches for storing mappings between logical addresses and physical addresses of the one or more non-volatile memory devices; and processing circuitry coupled with the one or more non-volatile memory devices and the one or more caches, wherein the processing circuitry is configured to cause the memory system to:
store an indication of an active region of the one or more non-volatile memory devices that is configured for use as part of a host performance booster mode;
enter a first power mode in accordance with storing the indication;
receive an access command that includes a physical address of the one or more non-volatile memory devices in the active region of the one or more non-volatile memory devices in accordance with entering the first power mode;
transition to a second power mode from the first power mode in accordance with receiving the access command;
determine whether the physical address of the access command is associated with the active region in accordance with the indication stored in the one or more non-volatile memory devices; and
perform, while the one or more non-volatile memory devices is operating in the second power mode, an operation using the physical address of the one or more non-volatile memory devices in accordance with receiving the access command and in accordance with determining that the physical address of the access command is associated with the active region.

11 . The memory system of claim 10 , wherein the processing circuitry is further configured to cause the memory system to:
refrain from performing, while the one or more non-volatile memory devices is operating in the second power mode, an operation using the physical address of the one or more non-volatile memory devices in accordance with determining that the physical address of the access command is not associated with the active region; and transmit an indication in accordance with determining that the physical address of the access command is not associated with the active region.

12 . The memory system of claim 10 , wherein the indication of the active region of the one or more non-volatile memory devices comprises a starting address and a quantity of addresses in the active region associated with one or more physical addresses of the one or more non-volatile memory devices, and the processing circuitry is further configured to cause the memory system to:
compare the physical address associated with the access command with the starting address and the quantity of addresses associated with the active region, wherein determining whether the physical address of the access command of the one or more non-volatile memory devices is associated with the active region is in accordance with comparing the physical address associated with the access command with the starting address and the quantity of addresses associated with the active region.

13 . The memory system of claim 10 , wherein the indication of the active region

Assignees

• Micron Technology Inc

Inventors

• Zhao Bin
• Wang Lingyun

Classifications

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title