Memory system and method of controlling nonvolatile memory

Patent metadata

Field	Value
Publication number	US-12547321-B2
Application number	US-202418592763-A
Country	US
Kind code	B2
Filing date	Mar 1, 2024
Priority date	Mar 2, 2023
Publication date	Feb 10, 2026
Grant date	Feb 10, 2026

Abstract

According to an embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first memory cell configured to nonvolatilely store data of a plurality of bits including a first bit and a second bit, and a second memory cell configured to nonvolatilely store data of at least one bit. The memory controller is configured to execute a save operation in accordance with reception of a command from a host, in the save operation, write first bit data to the second memory cell in a case where the first memory cell stores the first bit data as the first bit and does not store data as the second bit, and transmit, to the host, a completion response to the command after the first bit data has been written to the second memory cell.

First claim

What is claimed is:

1 . A memory system comprising:
a nonvolatile memory including a first memory cell configured to nonvolatilely store data of a plurality of bits, the plurality of bits including a first bit that is to be written to the first memory cell by a first write operation and a second bit that is to be written to the first memory cell by a second write operation, a second memory cell configured to nonvolatilely store data of at least one bit, a third memory cell configured to nonvolatilely store data of at least one bit, and a fourth memory cell configured to nonvolatilely store data of at least one bit; a first buffer; a second buffer; and a memory controller configured to:
execute a data erase operation to the first memory cell such that the first memory cell stores neither the first bit nor the second bit;
write first bit data to the first memory cell as the first bit by the first write operation;
generate a first error correction code corresponding to at least the first bit data;
write the first error correction code to the second buffer;
execute a save operation in accordance with reception of a command from a host; and
in the save operation, in a case that the save operation is executed at a first timing that is after the first write operation to write the first bit data to the first memory cell is executed and before the second write operation is executed to the first memory cell since execution of the data erase operation executed to the first memory cell,
write the first bit data to the second memory cell;
transmit, to the host, a completion response to the command after the first bit data has been written to the second memory cell; and
in a case where first write data that is scheduled to be written as the second bit to the first memory cell is stored in the first buffer:
read the first write data from the first buffer;
write the first write data read from the first buffer to the third memory cell;
generate a second error correction code based on at least one of the first bit data and the first write data; and
write the second error correction code to the fourth memory cell without writing, to the nonvolatile memory, the first error correction code stored in the second buffer.

2 . The memory system according to claim 1 , wherein
the memory controller is configured to:
read the first bit data from the first memory cell; and
write the first bit data read from the first memory cell to the second memory cell.

3 . The memory system according to claim 1 , wherein
the memory controller is further configured to:
manage the nonvolatile memory using a third table; and
in the save operation, omit the writing of the first bit data to the second memory cell in a case where information of the first bit data is registered in the third table.

4 . The memory system according to claim 1 , further comprising a third buffer,
wherein the nonvolatile memory further includes a fifth memory cell configured to nonvolatilely store data of a plurality of bits including a third bit and a fourth bit, and the memory controller is further configured to:
generate a third error correction code corresponding to at least the first bit data and second bit data stored as the third bit of the fifth memory cell; and
write the third error correction code to the third buffer.

5 . The memory system according to claim 4 , further comprising a fourth buffer,
wherein the memory controller is further configured to, in the save operation, generate a fourth error correction code based on at least one of the first bit data, the second bit data, and second write data in a case where the second write data that is scheduled to be written to the fourth bit of the fifth memory cell is stored in the fourth buffer.

6 . The memory system according to claim 5 , wherein
the nonvolatile memory further includes a sixth memory cell configured to nonvolatilely store data of at least one bit, and the memory controller is further configured to, in the save operation, write the fourth error correction code to the sixth memory cell without writing, to the nonvolatile memory, the third error correction code stored in the third buffer in a case where the third error correction code is stored in the nonvolatile memory.

7 . The memory system according to claim 5 , wherein
the nonvolatile memory further includes a seventh memory cell configured to nonvolatilely store data of at least one bit, and the memory controller is further configured to, in the save operation, write a fifth error correction code to the seventh memory cell in a case where the fifth error correction code corresponding to the second write data is stored in the third buffer.

8 . The memory system according to claim 1 , wherein
the nonvolatile memory includes a first memory area that includes the first memory cell and is not used for the save operation, and a second memory area that includes the second memory cell and is used for the save operation.

9 . The memory system according to claim 1 , wherein
a write operation to the first memory cell includes the first write operation of writing data as the first bit, and the second write operation of writing data as the second bit, and the memory controller is further configured to execute the second write operation based on the first bit data written as the first bit and the first write data that is scheduled to be written as the second bit.

10 . A memory system comprising:
a nonvolatile memory including a first memory cell configured to nonvolatilely store data of a plurality of bits, the plurality of bits including a first bit that is to be written to the first memory cell by a first write operation and a second bit that is to be written to the first memory cell by a second write operation, a second memory cell configured to nonvolatilely store data of at least one bit, and a third memory cell configured to nonvolatilely store data of at least one bit; a first buffer; and a memory controller is further configured to:
execute a data erase operation to the first memory cell such that the first memory cell stores neither the first bit nor the second bit;
write first bit data to the first memory cell as the first bit by the first write operation;
execute a save operation in accordance with reception of a command from a host;
manage, using a first table, data written from the first buffer to the third memory cell;
manage, using a second table, data written from the first memory cell to the second memory cell; and
in the save operation, in a case that the save operation is executed at a first timing that is after the first write operation to write the first bit data to the first memory cell is executed and before the second write operation is executed to the first memory cell since execution of the data erase operation executed to the first memory cell:
write the first bit data to the second memory cell in a case where information of the first bit data is not registered in the second table;
transmit, to the host, a completion response to the command after the first bit data has been written to the second memory cell; and
in a case where first write data that is scheduled to be written as the second bit to the first memory cell is stored in the first buffer:
read the first write data from the first buffer; and
write the first write data read from the first buffer to the third memory cell in a case where information of the first write data is not registered in the first table.

11 . The memory system according to claim 10 , wherein
the memory controller is further configured to register the information of the first write data in the fir

Assignees

• Kioxia Corp

Inventors

• Nishikawa Suguru
• Amaki Takehiko
• Igahara Shunichi
• Hida Toshikatsu
• Kojima Yoshihisa

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title