Information processing method, information processing apparatus, and program that combines multiple cooking steps
US-2025181831-A1 · Jun 5, 2025 · US
Information processing apparatus and control method
US12547227B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12547227-B2 |
| Application number | US-202418618185-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 27, 2024 |
| Priority date | May 22, 2023 |
| Publication date | Feb 10, 2026 |
| Grant date | Feb 10, 2026 |
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- Title
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Abstract
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An information processing apparatus includes a first processor, a second processor, an execution management unit configured to select a processor corresponding to a program whose execution is instructed, based on setting information indicating an execution processor for each program, and a power control unit configured to control an operation state based on power consumption of the first processor and the second processor, according to a power control mode selected from a plurality of levels of power control modes that differ in rated power. The power control unit is configured to stop access to the second processor, when changing the power control mode from a high power control mode whose rated power is higher than or equal to a predetermined rated power to a low power control mode whose rated power is lower than the predetermined rated power.
First claim
Opening claim text (preview).
The invention claimed is: 1 . An information processing apparatus comprising: a first processor; a second processor; an execution management unit configured to select a processor corresponding to a program whose execution is instructed, based on setting information indicating an execution processor for each program; and a power control unit configured to: control an operation state based on power consumption of the first processor and the second processor, according to a power control mode selected from a plurality of levels of power control modes that differ in rated power, stop access to the second processor, when changing the power control mode from a high power control mode whose rated power is higher than or equal to a predetermined rated power to a low power control mode whose rated power is lower than the predetermined rated power, and when instructed to change from the high power control mode to the low power control mode during execution of processing of a program using the second processor, output guidance information indicating: at least one of suspending the change to the low power control mode and resuming the processing of the program using the first processor, and ending the processing of the program. 2 . The information processing apparatus according to claim 1 , wherein the power control unit is configured to, when instructed to suspend the change to the low power control mode, wait without stopping the access to the second processor until the processing of the program using the second processor ends. 3 . The information processing apparatus according to claim 2 , wherein the power control unit is configured to set setting information indicating the second processor as an execution processor for the program. 4 . The information processing apparatus according to claim 3 , wherein the power control unit is configured to set setting information indicating the first processor as an execution processor for the program. 5 . The information processing apparatus according to claim 1 , wherein the power control unit is configured to, when instructed to resume the processing of the program using the first processor, stop the processing of the program using the second processor and thereafter resume the processing of the program using the first processor. 6 . The information processing apparatus according to claim 1 , wherein the first processor is an integrated graphics processing unit integrated with a central processing unit, and the second processor is an independent graphics processing unit. 7 . A control method for an information processing apparatus including a first processor and a second processor, comprising: selecting a processor corresponding to a program whose execution is instructed, based on setting information indicating an execution processor for each program; controlling an operation state based on power consumption of the first processor and the second processor, according to a power control mode selected from a plurality of levels of power control modes that differ in rated power; stopping access to the second processor, when changing the power control mode from a high power control mode whose rated power is higher than or equal to a predetermined rated power to a low power control mode whose rated power is lower than the predetermined rated power; when instructed to change from the high power control mode to the low power control mode during execution of processing of a program using the second processor, outputting guidance information indicating: at least one of suspending the change to the low power control mode and resuming the processing of the program using the first processor, and ending the processing of the program.
Assignees
Inventors
Classifications
Power management, i.e. event-based initiation of a power-saving mode · CPC title
Monitoring of events, devices or parameters that trigger a change in power modality · CPC title
by switching to a less power-consuming processor, e.g. sub-CPU · CPC title
by task scheduling · CPC title
by lowering clock frequency · CPC title
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- What does patent US12547227B2 cover?
- An information processing apparatus includes a first processor, a second processor, an execution management unit configured to select a processor corresponding to a program whose execution is instructed, based on setting information indicating an execution processor for each program, and a power control unit configured to control an operation state based on power consumption of the first proces…
- Who is the assignee on this patent?
- Lenovo Singapore Pte Ltd
- What technology area does this patent fall under?
- Primary CPC classification G06F1/26. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Feb 10 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).