Thin-film transistor array substrate with connection node and display device including the same

Patent metadata

Field	Value
Publication number	US-12543370-B2
Application number	US-202217652847-A
Country	US
Kind code	B2
Filing date	Feb 28, 2022
Priority date	Aug 24, 2012
Publication date	Feb 3, 2026
Grant date	Feb 3, 2026

Abstract

A thin-film transistor (TFT) array substrate including: a first conductive layer selected from an active layer, a gate electrode, a source electrode, and a drain electrode of a TFT; a second conductive layer in a layer different from the first conductive layer; and a connection node coupling the first conductive layer to the second conductive layer. Here, the TFT array has a node contact hole formed by: a first contact hole in the first conductive layer; and a second contact hole in the second conductive layer, the second contact hole being integral with the first contact hole and not being separated from the first contact hole by an insulating layer, and at least a portion of the connection node is in the node contact hole.

First claim

What is claimed is:

1 . A thin-film transistor (TFT) array substrate comprising:
a first conductive layer; a first insulating layer disposed on the first conductive layer and comprising a first opening; a second conductive layer disposed on the first insulating layer; a second insulating layer disposed on the second conductive layer and comprising a second opening; and a third conductive layer disposed on the second insulating layer, wherein the third conductive layer extends through the first opening and the second opening to directly contact the first conductive layer, and the third conductive layer extends through the second opening to directly contact the second conductive layer, wherein the first conductive layer does not overlap the entire second opening, wherein the first conductive layer and the second conductive layer are not in direct contact with each other in the second opening, and wherein the first opening and the second opening overlap each other in a cross-sectional view.

2 . The TFT array substrate of claim 1 , wherein the third conductive layer covers the entire second opening.

3 . The TFT array substrate of claim 1 , wherein the third conductive layer covers the entire first opening.

4 . The TFT array substrate of claim 1 , wherein a size of the second opening is larger than a size of the first opening in a plan view.

5 . The TFT array substrate of claim 4 , wherein a portion of a surface of the first insulating layer forming the first opening is connected to a portion of a surface of the second insulating layer forming the second opening without a step.

6 . A thin-film transistor (TFT) array substrate comprising:
a first conductive layer; a first insulating layer disposed on the first conductive layer and comprising a first opening; a second conductive layer disposed on the first insulating layer; a second insulating layer disposed on the second conductive layer and comprising a second opening; a third conductive layer disposed on the second insulating layer; and a TFT comprising an active layer, a gate electrode on the active layer, a source and drain electrodes on the active layer, wherein the first conductive layer and the second conductive layer are not in direct contact with each other in the second opening, wherein the first conductive layer is disposed on the same layer as a layer on which the active layer is formed, wherein the third conductive layer extends through the first opening and the second opening to directly contact the first conductive layer, and the third conductive layer extends through the second opening to directly contact the second conductive layer, and wherein the first conductive layer does not overlap the entire second opening.

7 . The TFT array substrate of claim 6 , wherein the third conductive layer is disposed on the same layer as a layer on which a data wire is formed, the data wire providing a data signal.

8 . The TFT array substrate of claim 6 , wherein the first conductive layer comprises a same material as the active layer.

9 . The TFT array substrate of claim 8 , wherein the first conductive layer comprises doped polysilicon.

10 . The TFT array substrate of claim 6 , wherein the second conductive layer is disposed on the same layer as a layer on which the gate electrode is formed.

11 . The TFT array substrate of claim 10 , wherein the second conductive layer comprises a same material as the gate electrode.

12 . The TFT array substrate of claim 10 , wherein the second conductive layer is disposed on the same layer as a layer on which a scan wire is formed, the scan wire providing a scan signal.

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Won-Se

Classifications

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title