Apparatus and method for multi-phase clock calibration in high-speed data communication systems

Patent metadata

Field	Value
Publication number	US-12542647-B2
Application number	US-202418784432-A
Country	US
Kind code	B2
Filing date	Jul 25, 2024
Priority date	Jul 25, 2024
Publication date	Feb 3, 2026
Grant date	Feb 3, 2026

Abstract

An apparatus for multiphase clock calibration for a transmitter in data communication systems includes a phase interpolator (PI) configured to receive a clock signal and generate multiphase clock signals with adjustable duty cycles and in-phase quadrature control. The apparatus may include a pattern generator coupled to the PI and configured to generate a pattern output based on a data signal sampled by the multiphase clock signals. The apparatus also includes a delay-adjust module coupled to the PI and configured to measure timing differences between the edges of a reference clock and the pattern output with adjustable delays. A phase detector is coupled to the pattern generator and configured to detect a phase error between the pattern output and the reference clock. A calibration controller is configured to provide controls to the PI and the delay-adjust module for adjusting delays to the reference clock and the pattern output to calibrate the multiphase clock signals.

First claim

What is claimed is:

1 . An apparatus for clock calibration, comprising:
a phase interpolator (PI) configured to receive a clock signal and generate multiphase clock signals; a pattern generator coupled to the PI and configured to generate a pattern output based on a data signal sampled by the multiphase clock signals with adjustable duty cycles and in-phase quadrature control; a delay-adjust module coupled to the PI and configured to measure timing differences between edges of a reference clock and the pattern output with adjustable delays; a phase detector (PD) coupled to the pattern generator and configured to detect a phase error between the pattern output and the reference clock; and a controller configured to provide controls to the PI and the delay-adjust module for adjusting phases of the reference clock and the pattern output to calibrate the multiphase clock signals.

2 . The apparatus of claim 1 , wherein the multiphase clock signals comprise clock signals having more than two phases.

3 . The apparatus of claim 1 , wherein the delay-adjust module comprises one of delay adjustable circuits comprising switches or transmission gate arrays for delay adjustment, voltage-controlled delay elements, capacitor delay elements, resistor delay elements, a phase-locked loop, or a delay-locked loop.

4 . The apparatus of claim 1 , wherein the PD comprises a circuit that is configured to distinguish phase differences of the clock signal, including a flip-flop circuit-based phase detector, an analog-to-digital converter-based phase detector, a phase frequency detector, an edge-triggered phase detector, a heterodyne phase detector, a time-to-digital converter-based phase detector, a multiplier-based phase detector, and a zero-crossing phase detector.

5 . The apparatus of claim 1 , wherein the pattern generator is configured to generate the pattern output having a rising edge synchronized with a rising edge of an in-phase clock of the multiphase clock signals and the next rising edge synchronized with a rising edge of an invert-phase clock of the multiphase clock signals.

6 . The apparatus of claim 5 , wherein the delay-adjust module is configured to measure a first timing difference between the rising edges of the reference clock and the pattern output and a second timing difference between the rising edges of the reference clock and the pattern output with a delay by half-cycle PI rotations and to perform an operation of subtracting the first timing difference from the second timing difference to extract duty-cycle errors of the multiphase clock signals.

7 . The apparatus of claim 6 , wherein the PD is configured to use ¾ of the maximum value of a PD output to detect the rising edge of the pattern output that is synchronized with the invert-phase clock and ¼ of the maximum value to detect the rising edge of the delayed pattern output that is synchronized with the in-phase clock.

8 . The apparatus of claim 7 , wherein the delay-adjust module is configured to measure a first timing difference between the rising edges of the reference clock and the pattern output and a second timing difference between the rising edges of the reference clock and the pattern output with a two-bit shift plus a delay by half-cycle PI rotations and to perform an operation of subtracting the first timing difference from the second timing difference to extract duty-cycle errors of the multiphase clock signals.

9 . The apparatus of claim 8 , wherein the PD is configured to use ¾ of the maximum value of a PD output to detect the rising edge of the pattern output that is synchronized with the invert-phase clock and ½ of the maximum value to detect the rising edge of bit-shifted delayed pattern output that is synchronized with an invert quadrature-phase clock.

10 . The apparatus of claim 1 , wherein the pattern generator is configured to generate the pattern output having one rising edge synchronized with a rising edge of an in-phase clock of the multiphase clock signals and the next rising edge synchronized with a rising edge of a quadrature-phase clock of the multiphase clock signals.

11 . The apparatus of claim 10 , wherein the delay-adjust module is configured to measure a first timing difference between the rising edges of the reference clock and the pattern output and a second timing difference between the rising edges of the reference clock and the pattern output with a delay by quarter-cycle PI rotations and to perform an operation of subtracting the first timing difference from the second timing difference to extract an in-phase-quadrature-phase mismatch of the multiphase clock signals.

12 . The apparatus of claim 10 , wherein the delay-adjust module is configured to measure a first timing difference between the rising edges of the reference clock and the pattern output and a second timing difference between the rising edges of the reference clock and the pattern output with one-bit shift plus a delay by quarter-cycle PI rotations and to perform an operation of subtracting the first timing difference from the second timing difference to extract an in-phase-quadrature-phase mismatch of the multiphase clock signals.

13 . The apparatus of claim 11 , wherein the delay-adjust module comprises a high pass filter associated with the operation of subtracting the first timing difference from the second timing difference to filter out noises having frequencies lower than an inversed time spent between measuring the first timing difference and measuring the second timing difference.

14 . The apparatus of claim 1 , wherein the PD comprises a low pass filter by averaging the detected phase errors sampled over time to filter out high-frequency noises based on a smoothy factor between 0 and 1.

15 . A serializer with multiphase clock calibration in a data transmission system comprising:
a clock input receiving a clock signal; a data input configured to receive data signals; multiplexers configured to convert data signals to serialized data; output drivers configured to drive the serialized data to a transmission channel; a phase interpolator configured to receive the clock signal and generate multi-phase clocks; a pattern generator coupled to the data input and the phase interpolator to generate a pattern output based on a data signal sampled by the multiphase clock signals; a delay-adjust module coupled to the phase interpolator and configured to measure timing differences between edges of a reference clock and the pattern output with adjustable delays; a phase detector coupled to the pattern generator and the transmitter output, and configured to detect a phase error between the pattern output and the reference clock; a calibration engine interfaced with the phase interpolator, the phase detector, and the delay-adjust module to control the phase interpolator and the delay-adjust module to correct duty-cycle errors (DCE) and in-phase quadrature-phase mismatches (IQM) in the multiphase clock signals by minimizing the phase error.

16 . The serializer of claim 15 , wherein the pattern generator is configured to generate a first pattern output having one rising edge synchronized with a rising edge of an in-phase clock of the multiphase clock signals and the next rising edge synchronized with a rising edge of an invert-phase clock of the multiphase clock signals, and generate a second pattern output having one rising edge synchronized with a rising edge of an in-phase clock of the multiphase clock signals and next rising edge synchronized with a rising edge of a quadrature-phase clock of the multiphase clock signal

Assignees

• Avago Tech Int Sales Pte Lid

Inventors

• Chung Sanghye
• Lee Seong-Ho
• Vasani Anand
• Jeon Hyung-Joon
• Iyer Arvindh
• Nidhi Nitin
• Kocaman Namik Kemal
• Li Yuanfang
• Jung Jun Won
• Chen Chung-Jue
• Yoon Taehun
• Yu George

Classifications

• H03K5/13

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title

• H04L7/02 Primary

  Speed or phase control by the received code signals, the signals containing no special synchronisation information {(H04L7/0075 takes precedence)} · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title