Semiconductor switch assembly having a monitoring function, energy system and vehicle

Patent metadata

Field	Value
Publication number	US-12540965-B2
Application number	US-202218558878-A
Country	US
Kind code	B2
Filing date	Apr 25, 2022
Priority date	May 11, 2021
Publication date	Feb 3, 2026
Grant date	Feb 3, 2026

Abstract

The invention relates to a semiconductor switch assembly, an energy system, and a vehicle. The semiconductor switch assembly includes a first semiconductor switch (S 11 ), a second semiconductor switch (S 12 ), a resistor ( 10 ), an input terminal ( 20 ), an output terminal ( 22 ), a reference potential terminal ( 24 ), and an analysis unit ( 30 ), the first semiconductor switch (S 11 ) and the second semiconductor switch (S 12 ) being connected in series between the input terminal ( 20 ) and the output terminal ( 22 ) and being designed to allow and prevent a current to flow between the input terminal ( 20 ) and the output terminal ( 22 ) on the basis of a triggering operation by the analysis unit ( 30 ). The resistor ( 10 ) is connected between the reference potential terminal ( 24 ) and a connection point ( 50 ) between the first semiconductor switch (S 11 ) and the second semiconductor switch (S 12 ). The analysis unit ( 30 ) is configured to determine, in the switched-off state of both semiconductor switches, a short circuit in the first semiconductor switch (S 11 ) when an input voltage (UE) between the input terminal ( 20 ) and the reference potential terminal ( 24 ) corresponds to a voltage drop (U 10 ) over the resistor ( 10 ), and a short circuit in the second semiconductor switch (S 12 ) when an output voltage (UA) between the output terminal ( 22 ) and the reference potential terminal ( 24 ) corresponds to a voltage drop (U 10 ) over the resistor ( 10 ).

First claim

The invention claimed is:

1 . A semiconductor switch assembly having a monitoring function and including:
a first semiconductor switch (S 11 ), a second semiconductor switch (S 12 ), a resistor ( 10 ), an input terminal ( 20 ), an output terminal ( 22 ), a reference potential terminal ( 24 ), and an analysis unit ( 30 )
wherein
the first semiconductor switch (S 11 ) and the second semiconductor switch (S 12 ):
are connected in series between the input terminal ( 20 ) and the output terminal ( 22 ) such that a drain terminal of the first semiconductor switch (S 11 ) is connected to the input terminal ( 20 ), a drain terminal of the second semiconductor switch (S 12 ) is connected to the output terminal ( 22 ), and a source terminal of the first semiconductor switch (S 11 ) is connected to a source terminal of the second semiconductor switch (S 12 ) at a connection point ( 50 ) for the two semiconductor switches (S 11 , S 12 ), and
are configured to allow and prevent a current to flow between the input terminal ( 20 ) and the output terminal ( 22 ) on the basis of a triggering operation by the analysis unit ( 30 ),

the resistor ( 10 ) is connected between the reference potential terminal ( 24 ) and the connection point ( 50 ) of the first semiconductor switch (S 11 ) and the second semiconductor switch (S 12 ), and
the analysis unit ( 30 ) is configured, in a state in which the first semiconductor switch (S 11 ) and the second semiconductor switch (S 12 ) are open:
to determine a short circuit in the first semiconductor switch (S 11 ) when an output voltage (UA) between the output terminal ( 20 ) and the reference potential terminal ( 24 ) substantially corresponds to a voltage drop (U 10 ) over the resistor ( 10 ), and
to determine a short circuit in the second semiconductor switch (S 12 ) when an output voltage (UA) between the output terminal ( 22 ) and the reference potential terminal ( 24 ) substantially corresponds to a voltage drop (U 10 ) over the resistor ( 10 ),

wherein the analysis unit ( 30 ) is configured to:
measure a current (IA) flowing between the input terminal ( 20 ) and the output terminal ( 22 ) and
verify compliance with respective target switching states for the first semiconductor switch (S 11 ) and the second semiconductor switch (S 12 ) on the basis of on an expected relationship between the measured current (IA) and a voltage (US 1 ) between the input terminal ( 20 ) and the output terminal ( 22 ), and

wherein,
a series circuit comprising a third semiconductor switch (S 13 ) and a fourth semiconductor switch (S 14 ) arranged in parallel with the series circuit comprising the first semiconductor switch (S 11 ) and the second semiconductor switch (S 12 ), wherein the third semiconductor switch (S 13 ) and the fourth semiconductor switch (S 14 ) are, according to the first semiconductor switch (S 11 ) and the second semiconductor switch (S 12 ), connected between the input terminal ( 20 ) and the output terminal ( 22 ),
a connection point of respective source terminals of the third semiconductor switch (S 13 ) and the fourth semiconductor switch (S 14 ) is connected to the connection point ( 50 ) of the source terminals of the first semiconductor switch (S 11 ) and the second semiconductor switch (S 12 ), and
the analysis unit ( 30 ) is configured to perform a short circuit monitoring and target switching state monitoring together for the first semiconductor switch (S 11 ), the second semiconductor switch (S 12 ), the third semiconductor switch (S 13 ), and the fourth semiconductor switch (S 14 ).

2 . The semiconductor switch assembly according to claim 1 , wherein the analysis unit ( 30 ) is configured to trigger the first semiconductor switch (S 11 ) and the second semiconductor switch (S 12 ) such that a current flow between the input terminal ( 20 ) and the output terminal ( 22 ) is enabled bidirectionally or unidirectionally.

3 . The semiconductor switch assembly according to claim 1 , wherein
a current path including the first semiconductor switch (S 11 ) and the second semiconductor switch (S 12 ) is a first current path ( 60 ) of the semiconductor switch assembly, the semiconductor switch assembly comprises at least one second current path ( 62 ) different from the first current path ( 60 ) between the input terminal ( 20 ) and the output terminal ( 22 ) having a series connection comprising a fifth semiconductor switch (S 21 ) and a sixth semiconductor switch (S 22 ), the resistor is a first resistor ( 10 ), a second resistor ( 12 ) is connected between the reference potential terminal ( 24 ) and a connection point of the fifth semiconductor switch (S 21 ) and the sixth semiconductor switch (S 22 ), and the analysis unit ( 30 ) is configured to perform short circuit monitoring and target switch state monitoring for the fifth semiconductor switch (S 21 ) and the sixth semiconductor switch (S 22 ) based on a voltage drop over the second resistor ( 12 ).

4 . The semiconductor switch assembly according to claim 1 , wherein the analysis unit ( 30 ) is configured, when determining compliance with the respective target switching states for each of the semiconductor switches (S 11 , S 12 , S 13 , S 14 , S 21 , S 22 ) being monitored:
to take into account a first predefined tolerance range ( 70 ) for the expected current-voltage relationship, which applies when the semiconductor switches (S 11 , S 12 , S 13 , S 14 , S 21 , S 22 ) being monitored are triggered such that a bidirectional current flow between the input terminal ( 20 ) and the output terminal ( 22 ) is enabled, and to take into account a second predefined tolerance range ( 72 ) for the expected current-voltage relationship, which applies when the semiconductor switches (S 11 , S 12 , S 13 , S 14 , S 21 , S 22 ) being monitored are triggered such that a unidirectional current flow between the input terminal ( 20 ) and the output terminal ( 22 ) is enabled.

5 . The semiconductor switch assembly according to claim 4 , wherein the analysis unit ( 30 ) is configured to adapt the first tolerance range ( 70 ) and the second tolerance range ( 72 ) as a function of:
each of the current paths used ( 60 , 62 ), and/or a number of parallel circuits of semiconductor switches (S 11 , S 12 , S 13 , S 14 , S 21 , S 22 ) used within a respective current path ( 60 , 62 ), and/or a current-temperature relationship applicable to the respective semiconductor switches (S 11 , S 12 , S 13 , S 14 , S 21 , S 22 ), and/or aging conditions of respective semiconductor switches (S 11 , S 12 , S 13 , S 14 , S 21 , S 22 ).

6 . The semiconductor switch assembly according to claim 1 , wherein the analysis unit ( 30 ) is configured to determine a type and/or an execution speed of a fault response which is initiated in response to a determined fault state of at least one semiconductor switch (S 11 , S 12 , S 13 , S 14 , S 21 , S 22 ) as a function of:
an amount of a deviation from the first tolerance range ( 70 ) and/or from the second tolerance range ( 72 ), and/or a type of the fault state present.

7 . The semiconductor switch assembly according to claim 1 , wherein the semiconductor switch assembly is configured to switch voltages of up to 1000 V.

8 . An energy system comprising:
a semiconductor switch assembly according to claim 1 , a first electrical energy source ( 80 ) connected between the input terminal ( 20 ) and the reference potential terminal ( 24 ) such that an electrical voltage (UE) is applied between the input terminal ( 20 ) and the reference potential terminal ( 24 ), and an electrical consumer ( 90 ) and/or a switchable second electrical energy source ( 85 ) connected between the output terminal ( 22 )

Assignees

• Bosch Gmbh Robert

Inventors

• Sautter Siegbert
• Kaupp Patrick
• Swoboda Johannes
• Kohn Peter
• Rueck Sebastian
• Schaedlich Thomas

Classifications

• H03K17/08104

  in field-effect transistor switches (H03K17/0812, H03K17/0814 take precedence) · CPC title

• G01R31/27

  Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements {(testing printed circuit boards G01R31/2801)} · CPC title

• G01R31/2621 Primary

  for testing field effect transistors, i.e. FET's · CPC title

• G01R31/3277

  of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches · CPC title

• H03K17/6874

  in a symmetrical configuration · CPC title