Device and method for monitoring power supply voltage of electronic circuit

Patent metadata

Field	Value
Publication number	US-12540959-B2
Application number	US-202418604457-A
Country	US
Kind code	B2
Filing date	Mar 13, 2024
Priority date	Mar 13, 2023
Publication date	Feb 3, 2026
Grant date	Feb 3, 2026

Abstract

Embodiments of the present disclosure provide a device and a method for monitoring power supply voltage of an electronic circuit. The device comprising: a voltage regulator configured to process the power supply voltage to generate a predetermined voltage; a critical timing generation module powered by the predetermined voltage and configured to generate a critical timing signal based on an original clock signal and a delay control signal, the critical timing signal being alternately in a first level state and a second level state; a control signal adjustment module configured to adjust the delay control signal based on the critical timing signal, wherein in a case that the critical timing signal is in the first level state, the delay control signal is increased, and in a case that the critical timing signal is in the second level state, the delay control signal is decreased; and a power supply drop sensing module powered by the power supply voltage and configured to generate a drop indication signal based on the original clock signal and the delay control signal, the drop indication signal indicating whether the power supply voltage drops below the predetermined voltage.

First claim

What is claimed is:

1 . A device for monitoring a power supply voltage of an electronic circuit, comprising:
a voltage regulator configured to process the power supply voltage to generate a predetermined voltage; a critical timing generation module powered by the predetermined voltage and configured to generate a critical timing signal based on an original clock signal and a delay control signal, the critical timing signal being alternately in a first level state and a second level state; a control signal adjustment module configured to adjust the delay control signal based on the critical timing signal, wherein in a case that the critical timing signal is in the first level state, the delay control signal is increased, and in a case that the critical timing signal is in the second level state, the delay control signal is decreased; and a power supply drop sensing module powered by the power supply voltage and configured to generate a drop indication signal based on the original clock signal and the delay control signal, the drop indication signal indicating whether the power supply voltage drops below the predetermined voltage.

2 . The device of claim 1 , wherein the critical timing generation module comprises:
a first frequency divider configured to divide a frequency of the original clock signal to generate a first frequency division signal; a first delay unit configured to delay the first frequency division signal to generate a first delay signal, wherein a delay amount provided by the first delay unit is controlled by the delay control signal; and a timing determination unit configured to generate the critical timing signal based on a phase relationship between the first frequency division signal and the first delay signal, wherein in a case that a phase difference of the first frequency division signal and the first delay signal is half a cycle, the critical timing signal is in the second level state, and in a case that the phase difference of the first frequency division signal and the first delay signal does not reach half a cycle, the critical timing signal is in the first level state.

3 . The device of claim 2 , wherein the timing determination unit comprises:
a first phase discriminator configured to identify the phase difference between the first frequency division signal and the first delay signal to generate a first phase discrimination signal representing the phase difference, wherein the first phase discrimination signal or an inversion signal of the first phase discrimination signal is used as the critical timing signal.

4 . The device of claim 2 , wherein the power supply drop sensing module comprises:
a second frequency divider configured to divide a frequency of the original clock signal to generate a second frequency division signal; a second delay unit configured to delay the second frequency division signal to generate a second delay signal, wherein a delay amount provided by the second delay unit is controlled by the delay control signal; and a power supply drop determination module configured to generate the drop indication signal based on a phase relationship between the second frequency division signal and the second delay signal.

5 . The device of claim 4 , wherein the power supply drop determination module comprises:
a second phase discriminator configured to identify a phase difference between the second frequency division signal and the second delay signal to generate a second phase discrimination signal representing the phase difference, wherein the second phase discrimination signal or an inversion signal of the second phase discrimination signal is used as the drop indication signal.

6 . The device of claim 4 , wherein the second frequency divider and the first frequency divider have the same frequency division ratio.

7 . The device of claim 4 , wherein the second delay unit and the first delay unit have the same circuit structure.

8 . The device of claim 1 , wherein the control signal adjustment module comprises a digital state machine, the digital state machine has a first adjustment state for increasing the delay control signal and a second adjustment state for decreasing the delay control signal, wherein in a case that the critical timing signal is in the first level state, the digital state machine switches to the first adjustment state, and in a case that the critical timing signal is in the second level state, the digital state machine switches to the second adjustment state.

9 . The device of claim 1 , wherein the voltage regulator comprises:
a low-pass filter configured to perform low-pass filtering on the power supply voltage to generate a filtered voltage; an amplifier having a first input receiving the filtered voltage; and a transistor and capacitor connected in series between the power supply voltage and ground, wherein a control end of the transistor is connected to an output end of the amplifier, an intermediate node between the transistor and the capacitor is connected to a second input of the amplifier, the intermediate node provides the predetermined voltage.

10 . A method for monitoring a power supply voltage of an electronic circuit, comprising:
processing the power supply voltage to generate a predetermined voltage; at the predetermined voltage, generating a critical timing signal based on an original clock signal and a delay control signal, the critical timing signal being alternately in a first level state and a second level state; adjusting the delay control signal based on the critical timing signal, wherein in a case that the critical timing signal is in the first level state, the delay control signal is increased, and in a case that the critical timing signal is in the second level state, the delay control signal is decreased; and at the power supply voltage, generating a drop indication signal based on the original clock signal and the delay control signal, the drop indication signal indicating whether the power supply voltage drops below the predetermined voltage.

11 . The method of claim 10 , wherein generating a critical timing signal based on an original clock signal and a delay control signal comprises:
dividing a frequency of the original clock signal to generate a first frequency division signal; delaying the first frequency division signal to generate a first delay signal, wherein a delay amount on the first frequency division signal is controlled by the delay control signal; and generating the critical timing signal based on a phase relationship between the first frequency division signal and the first delay signal, wherein in a case that a phase difference of the first frequency division signal and the first delay signal is half a cycle, the critical timing signal is in the second level state, and in a case that the phase difference of the first frequency division signal and the first delay signal does not reach half a cycle, the critical timing signal is in the first level state.

12 . The method of claim 11 , wherein generating the critical timing signal based on a phase relationship between the first frequency division signal and the first delay signal comprises:
identifying the phase difference between the first frequency division signal and the first delay signal to generate a first phase discrimination signal representing the phase difference, wherein the first phase discrimination signal or an inversion signal of the first phase discrimination signal is used as the critical timing signal.

13 . The method of claim 11 , wherein generating a drop indication signal based on the original clock signal and the delay control signal compris

Assignees

• Beijing Youzhuju Network Tech Co Ltd
• Lemon Inc

Inventors

• Guo Junyan
• Dong Weifeng
• Zhang Mingming
• Zhang Chuang
• Zhang Junmou
• Lu Shan
• Wang Jian

Classifications

• H03K2005/00078

  Fixed delay · CPC title

• H03K5/00006

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title

• G01R19/16576 Primary

  comparing DC or AC voltage with one threshold (G01R19/16514, G01R19/16519, G01R19/16528, G01R19/16533 and G01R19/1659 take precedence) · CPC title

• G01R25/005 Primary

  Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller, or for passing one of the input signals as output signal · CPC title

• G01R19/16538

  in AC or DC supplies (G01R19/16519 and G01R19/16528 take precedence) · CPC title