Signal analyzing circuit and method for auto setting an oscilloscope
US-2019212369-A1 · Jul 11, 2019 · US
US12540953B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12540953-B2 |
| Application number | US-202217935301-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 26, 2022 |
| Priority date | Sep 26, 2022 |
| Publication date | Feb 3, 2026 |
| Grant date | Feb 3, 2026 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
The present disclosure provides a measurement application device comprising at least one signal acquisition interface configured to acquire an analog input signal and output a digital input signal, a first decimator for each signal acquisition interface, each one of the first decimators being configured to reduce the number of samples of the respective digital input signal and output a first decimated digital input signal, at least one second decimator for each signal acquisition interface, each one of the second decimators being configured to reduce the number of samples of the respective digital input signal and output a second decimated digital input signal, and at least one decoder for each one of the second decimators, each one of the decoders being configured to decode the respective second decimated digital input signal according to a respective protocol and provide a respective decoded input signal.
Opening claim text (preview).
What is claimed is: 1 . A measurement application device comprising: at least one signal acquisition interface configured to acquire an analog input signal and output a digital input signal; a first decimator for each signal acquisition interface, each one of the first decimators being coupled to the respective one of the signal acquisition interfaces, each one of the first decimators being configured to reduce the number of samples of the respective digital input signal and output a first decimated digital input signal; at least one second decimator for each signal acquisition interface, each one of the second decimators being coupled to the respective one of the signal acquisition interfaces, each one of the second decimators being configured to reduce the number of samples of the respective digital input signal and output a second decimated digital input signal; and at least one decoder for each one of the second decimators, each one of the decoders being coupled to the respective one of the second decimators, and each one of the decoders being configured to decode the respective second decimated digital input signal according to a respective protocol and provide a respective decoded input signal. 2 . The measurement application device according to claim 1 , wherein each one of the first decimators operates on a first decimation factor, and wherein each one of the second decimators operates on a second decimation factor, wherein the second decimation factor is higher than the first decimation factor, especially two times higher, three times higher, five times higher, eight times higher, or ten times higher. 3 . The measurement application device according to claim 1 , further comprising for at least one of the first decimators a first data memory that is configured to store the respective first decimated digital input signal. 4 . The measurement application device according to claim 3 , wherein the first data memory comprises an acquisition memory of the measurement application device. 5 . The measurement application device according to claim 3 , further comprising: for each one of the decoders a second data memory that is configured to store the respective decoded input signal; a first trigger signal generator for at least one of the decoders that is coupled to the respective decoder for receiving the respective decoded input signal and to the second data memory for controlling data storage in the second data memory; and a second trigger signal generator for at least one of the first decimators that is coupled to the respective first decimator for receiving the respective first decimated digital input signal and to the respective first data memory for controlling data storage in the respective first data memory. 6 . The measurement application device according to claim 5 , further comprising a second trigger controller that is coupled to an output of at least one of the first trigger signal generators and an output of at least one of the second trigger signal generators, and that is configured to generate a combined trigger signal. 7 . The measurement application device according to claim 6 , wherein the second trigger controller comprises a second trigger logic circuitry that receives input trigger signals, and applies at least one of an OR function, an AND function, an IF function, a state machine, and a timer to the received input trigger signals to generate a combined trigger signal. 8 . The measurement application device according to claim 3 , further comprising a second data memory that is configured to store the respective decoded input signal for at least one of the decoders; and further comprising a third data memory that is coupled to one of the first data memories and one of the second data memories that store data that is based on the same digital input signal. 9 . The measurement application device according to claim 1 , further comprising for at least one of the decoders a second data memory that is configured to store the respective decoded input signal. 10 . The measurement application device according to claim 9 , wherein the second data memory comprises a remote memory that is coupled to the respective decoders via a data network. 11 . The measurement application device according to claim 9 , wherein the second data memory comprises a first memory section and a second memory section, wherein the second data memory is configured to alternatively store the respective decoded input signal in the first memory section and the second memory section, and output the respective decoded input signal from the memory section that is currently not written to during a read access to the second data memory. 12 . The measurement application device according to claim 9 , further comprising a first trigger signal generator for at least one of the decoders, wherein the first trigger signal generator is coupled to the respective decoder for receiving the respective decoded input signal, and to the second data memory for controlling data storage in the second data memory. 13 . The measurement application device according to claim 12 , comprising one of: at least two first trigger signal generators coupled to the same one of the decoders; or at least two decoders coupled to the same one of the second decimators, and a first trigger signal generator for each one of the at least two decoders. 14 . The measurement application device according to claim 13 , further comprising a first trigger controller that is coupled to an output of each one of the first trigger signal generators that are coupled to the same one of the decoders or to the at least two decoders that are coupled to the same one of the second decimators, and that is configured to generate a combined channel trigger signal. 15 . The measurement application device according to claim 14 , wherein the first trigger controller comprises a first trigger logic circuitry that receives input trigger signals, and applies at least one of an OR function, an AND function, an IF function, a state machine, and a timer to the received input trigger signals to generate a combined trigger signal. 16 . The measurement application device according to claim 1 , comprising: at least two signal acquisition interfaces; at least one second decimator for each one of the at least two signal acquisition interfaces; and at least one decoder for each one of the second decimators. 17 . The measurement application device according to claim 16 , further comprising one first decimator for each one of the at least two signal acquisition interfaces. 18 . The measurement application device according to claim 16 , further comprising a signal bridge that provides the second decimated digital input signal from at least one of the second decimators or the decoded input signal from the respective at least one decoder to at least one other of the decoders. 19 . The measurement application device according to claim 1 , further comprising a synchronization controller configured to timely synchronize at least one of the digital input signals, the first decimated digital input signals, the second decimated digital input signals, and the decoded input signals. 20 . The measurement application device according to claim 1 , further comprising a waveform signal generator that is configured to generate one of the first decimated digital input signals based on at least part of one of the decoded input signals. 21 . The measurement application d
for displaying sampled signals by using digital processors by intermediate A.D. and D.A. convertors (control circuits for CRT indicators) · CPC title
Software therefor · CPC title
for sampling · CPC title
Arrangements for displaying electric variables or waveforms · CPC title
Circuits therefor · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.