Display panel and electronic apparatus including the same

Patent metadata

Field	Value
Publication number	US-12538680-B2
Application number	US-202217891505-A
Country	US
Kind code	B2
Filing date	Aug 19, 2022
Priority date	Nov 8, 2021
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

A display panel and an electronic apparatus including the display panel are provided. The display panel includes a base layer including a display area and a non-display area, signal lines disposed in a first direction, each of the signal lines extending in a second direction intersecting the first direction, and connection patterns. Each of the connection patterns include a first line electrically connected to at least one of the signal lines through a contact portion and extending in the first direction, and a second line electrically connected to the first line and extending in the second direction. The contact portion between the first line and the at least one of signal lines is disposed in the display area, and the first lines of the connection patterns have a same length.

First claim

What is claimed is:

1 . A display panel comprising:
a base layer comprising a display area and a non-display area; signal lines disposed in a first direction, each of the signal lines extending in a second direction intersecting the first direction; and connection patterns comprising first lines and second lines, wherein each of the first lines is electrically connected to at least one of the signal lines through a contact portion and extends in the first direction, each of the second lines is electrically connected to a corresponding first line among the first lines and extends in the second direction, the contact portion between the first lines and the signal lines is disposed in the display area, the first lines of the connection patterns are disposed in the display area and have a same length, and the connection patterns do not overlap each other in a plan view, wherein the signal lines comprise:
signal lines of a first group each electrically connected to the first lines of the connection patterns; and
signal lines of a second group insulated from the signal lines of the first group and intersecting at least one of the first lines of the connection patterns.

2 . The display panel of claim 1 , wherein
the second lines of the connection patterns are disposed between the signal lines in a plan view.

3 . The display panel of claim 1 , wherein the first lines of the connection patterns and the second lines of the connection patterns are disposed on different layers.

4 . The display panel of claim 1 , wherein the first lines and the second lines of the connection patterns are disposed on a same layer and are integral with each other.

5 . The display panel of claim 1 , wherein the second lines of the connection patterns and the signal lines are disposed on a same layer.

6 . The display panel of claim 1 , wherein
each of the first lines intersects at least one of the signal lines in a plan view, and each of the first lines has a same number of overlapping signal lines in a plan view.

7 . The display panel of claim 1 , wherein
the base layer comprises sides extending in the second direction, and the signal lines of the first group are disposed closer to the sides of the base layer than the signal lines of the second group.

8 . The display panel of claim 1 , further comprising:
a load block electrically connected to at least one of the signal lines of the second group.

9 . The display panel of claim 8 , wherein the load block comprises at least one capacitor.

10 . The display panel of claim 9 , wherein
the at least one capacitor comprises a plurality of capacitors and electrically connected to different signal lines of the second group, respectively, the plurality of capacitors comprise:
a first capacitor electrically connected to a first signal line among the signal lines of the second group; and
a second capacitor electrically connected to a second signal line among the signal lines of the second group,
the first signal line is disposed closer to the signal lines of the first group than the second signal line in the first direction, and a capacitance of the first capacitor is larger than a capacitance of the second capacitor.

11 . The display panel of claim 8 , wherein
the load block comprises at least one resistance compensation pattern, and the at least one resistance compensation pattern comprises:
a first portion and a second portion each electrically connected to a corresponding signal line among the signal lines of the second group and extending in the first direction; and
a third portion electrically connected to the first portion and the second portion and extending in the second direction.

12 . The display panel of claim 11 , wherein the first portion, the second portion, and the third portion are disposed on different layers.

13 . The display panel of claim 11 , wherein the first portion, the second portion, and the first lines of the connection patterns are disposed on a same layer.

14 . The display panel of claim 11 , wherein
the at least one resistance compensation pattern comprises a plurality of resistance compensation patterns and electrically connected to different signal lines of the second group, respectively, the plurality of resistance compensation patterns comprise:
a first resistance compensation pattern electrically connected to a first signal line among the signal lines of the second group; and
a second resistance compensation pattern electrically connected to a second signal line among the signal lines of the second group,
the first signal line is disposed closer to the signal lines of the first group than the second signal line in the first direction, and a resistance of the first resistance compensation pattern is larger than a resistance of the second resistance compensation pattern.

15 . The display panel of claim 14 , wherein a sum of lengths of a first portion and a second portion of the first resistance compensation pattern is greater than a sum of lengths of a first portion and a second portion of the second resistance compensation pattern.

16 . The display panel of claim 14 , wherein
each of the first portion of the first resistance compensation pattern and the first portion of the second resistance compensation pattern overlaps at least one of the signal lines in a plan view, and a number of signal lines overlapping the first portion of the first resistance compensation pattern in a plan view is greater than a number of signal lines overlapping the first portion of the second resistance compensation pattern in a plan view.

17 . An electronic apparatus comprising:
a display panel including:
a base layer;
a circuit element layer disposed on the base layer; and
a display element layer disposed on the circuit element layer,
wherein the circuit element layer comprises: signal lines disposed on the base layer, disposed in a first direction, and each of the signal lines extending in a second direction intersecting the first direction; connection patterns each comprising:
a first line extending in the first direction; and
a second line electrically connected to the first line and extending in the second direction; and
a load block, wherein the signal lines comprise:
signal lines of a first group each electrically connected to the first lines of the connection patterns;
signal lines of a second group insulated from the signal lines of the first group and intersecting the first lines of the connection patterns; and
signal lines of a third group insulated from the signal lines of the second group and spaced apart from the connection patterns,
the load block is connected to at least one of the signal lines of the second group, and the first lines of the connection patterns have a same length.

18 . The electronic apparatus of claim 17 , further comprising:
an input sensing layer disposed on the display panel that senses an external input.

19 . The electronic apparatus of claim 17 , further comprising:
a camera module disposed below the display panel.

20 . A display panel comprising:
a base layer; signal lines disposed on the base layer, disposed in a first direction, and each of the signal lines extending in a second direction intersecting the first direction; connection patterns each comprising:
a first line extending in the first direction; and
a second line electrically connected to the first line and extending in the second direction; and
resistanc

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Jaewoo
• Lee Yongsu
• Lee Seung-Jun

Classifications

• H10K59/1315 Primary

  comprising structures specially adapted for lowering the resistance · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10K59/65

  OLEDs integrated with inorganic image sensors · CPC title

• H10K59/40

  OLEDs integrated with touch screens · CPC title