Array substrate, display apparatus, and connection pad

Patent metadata

Field	Value
Publication number	US-12538574-B2
Application number	US-202117904748-A
Country	US
Kind code	B2
Filing date	Oct 18, 2021
Priority date	Oct 18, 2021
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

An array substrate having a connection pad in a connection pad area is provided. The connection pad includes a plurality of first probe contact pads, a plurality of second probe contact pads, a plurality of first connection lines coupled to the plurality of first probe contact pads, respectively, and a plurality of second connection lines coupled to the plurality of second probe contact pads, respectively; the plurality of first connection lines and the plurality of second connection lines being in two different layers. A total number of conductive layers electrically connected to a respective first connection line of the plurality of first connection lines is different from a total number of conductive layers electrically connected to a respective second connection line of the plurality of second connection lines.

First claim

What is claimed is:

1 . An array substrate, comprising a connection pad in a connection pad area;
wherein the connection pad comprises a plurality of first probe contact pads, a plurality of second probe contact pads, a plurality of first connection lines coupled to the plurality of first probe contact pads, respectively, and a plurality of second connection lines coupled to the plurality of second probe contact pads, respectively; the plurality of first connection lines and the plurality of second connection lines being in two different layers; and a total number of conductive layers electrically connected to a respective first connection line of the plurality of first connection lines is different from a total number of conductive layers electrically connected to a respective second connection line of the plurality of second connection lines; wherein the connection pad further comprises a plurality of third probe contact pads, and a plurality of third connection lines coupled to the plurality of third probe contact pads, respectively; the plurality of first connection lines, the plurality of second connection lines, and the plurality of third connection lines being in three different layers; and a total number of conductive layers electrically connected to a respective first connection line of the plurality of first connection lines is different from a total number of conductive layers electrically connected to a respective third connection line of the plurality of third connection lines.

2 . The array substrate of claim 1 , comprising:
a base substrate; a second conductive layer on the base substrate; and a first conductive layer on a side of the second conductive layer away from the base substrate; wherein the first conductive layer comprises a first-first portion in a display area of the array substrate and a second-first portion in the connection pad area; the second conductive layer comprises a first-second portion in the display area and a second-second portion in the connection pad area; the second-first portion comprises the plurality of first connection lines; and the second-second portion comprises the plurality of second connection lines.

3 . The array substrate of claim 2 , further comprising an insulating layer between the second-first portion and the second-second portion;
wherein the insulating layer comprises an inter-layer dielectric layer, or a buffer layer, or a combination of the inter-layer dielectric layer and the buffer layer.

4 . The array substate of claim 2 , wherein the first conductive layer and the second conductive layer are two different layers selected from a gate metal layer, a source-drain electrode layer, or a light shielding layer.

5 . The array substrate of claim 2 , wherein the second-first portion further comprises a plurality of first relay electrodes in a same layer as the plurality of first connection lines;
wherein a respective first relay electrode of the plurality of first relay electrodes connects a respective second probe contact pad to a respective second connection line.

6 . The array substrate of claim 5 , wherein the first-first portion comprises a plurality of source electrodes and a plurality of drain electrodes of a plurality of thin film transistors; and
the plurality of source electrodes and the plurality of drain electrodes are in a same layer as the plurality of first connection lines and the plurality of first relay electrodes.

7 . The array substrate of claim 2 , wherein the first-second portion comprises a plurality of gate lines, and a plurality of gate electrodes of a plurality of thin film transistors, respectively; and
the plurality of gate lines and the plurality of gate electrodes are in a same layer as the plurality of second connection lines.

8 . The array substrate of claim 2 , wherein the array substrate further comprises a third conductive layer on a side of the second conductive layer closer to the base substrate;
wherein the third conductive layer comprises a first-third portion in the display area and a second-third portion in the connection pad area; and the second-third portion comprises the plurality of third connection lines.

9 . The array substrate of claim 8 , wherein the second-first portion further comprises a plurality of second relay electrodes in a same layer as the plurality of first connection lines;
wherein a respective second relay electrode of the plurality of second relay electrodes connects a respective third probe contact pad to a respective third connection line.

10 . The array substrate of claim 8 , wherein the first-third portion comprises a plurality of light shields in a same layer as the plurality of third connection lines; and
an orthographic projection of a respective light shield on the base substrate covers a respective active layer of a respective thin film transistor.

11 . The array substrate of claim 8 , further comprising:
an inter-layer dielectric layer between the second-first portion and the second-second portion; and a buffer layer between the second-second portion and the second-third portion.

12 . The array substrate of claim 8 , wherein the first conductive layer is a source-drain electrode layer;
the second conductive layer is a gate metal layer; and the third conductive layer is a light shielding layer.

13 . The array substrate of claim 1 , wherein an orthographic projection of the respective first connection line on a base substrate is non-overlapping with an orthographic projection of the respective second connection line on the base substrate;
the orthographic projection of the respective first connection line on the base substrate is non-overlapping with an orthographic projection of a respective third connection line on the base substrate; and the orthographic projection of the respective second connection line on the base substrate is non-overlapping with the orthographic projection of the respective third connection line on the base substrate.

14 . The array substrate of claim 1 , wherein an orthographic projection of the respective first connection line on a base substrate is at least partially overlapping with an orthographic projection of the respective second connection line on the base substrate;
the orthographic projection of the respective first connection line on the base substrate is at least partially overlapping with an orthographic projection of a respective third connection line on the base substrate; and the orthographic projection of the respective second connection line on the base substrate is at least partially overlapping with the orthographic projection of the respective third connection line on the base substrate.

15 . The array substrate of claim 1 , wherein an orthographic projection of the respective first connection line on a base substrate is non-overlapping with an orthographic projection of the respective second connection line on the base substrate.

16 . The array substrate of claim 1 , wherein an orthographic projection of the respective first connection line on a base substrate is at least partially overlapping with an orthographic projection of the respective second connection line on the base substrate.

17 . An array substrate, comprising a connection pad in a connection pad area;
wherein the connection pad comprises a plurality of first probe contact pads, a plurality of second probe contact pads, a plurality of first connection lines coupled to the plurality of first probe contact pads, respectively, and a plurality of second connection lines coupl

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Guoying
• Xu Pan
• Zhang Dacheng
• Zhang Xing
• Han Ying
• Luo Chengyuan
• Song Zhen

Classifications

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title