Trench-type power device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12538563-B2
Application number	US-202218091547-A
Country	US
Kind code	B2
Filing date	Dec 30, 2022
Priority date	Dec 30, 2021
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

Disclosed is a trench-type power device and a manufacturing method thereof. The trench-type power device comprises: a semiconductor substrate; a drift region located on the semiconductor substrate; a first trench and a second trench located in the drift region; a gate stack located in the first trench; and Schottky metal located on a side wall of the second trench, wherein the Schottky metal and the drift region form a Schottky barrier diode. The trench-type power device adopts a double-trench structure, which combines a trench-type MOSFET with the Schottky barrier diode and forms the Schottky metal on the side wall of the trench, so that the performance of the power device can be improved, and the unit area of the power device can be reduced.

First claim

What is claimed is:

1 . A trench-type power device, comprising:
a semiconductor substrate; a drift region on the semiconductor substrate; a first trench and a second trench located in the drift region; a gate stack located in the first trench; and Schottky metal located on a side wall of the second trench, wherein the Schottky metal and the drift region form a Schottky barrier diode, wherein the trench-type power device further comprises: a conductive channel, which is formed by filling a conductive material in the second trench and is positionally separated from the drift region by the Schottky metal, which is different from the conductive material; a doped region located below a bottom of the second trench, wherein a dopant type of the doped region is opposite to that of the drift region; and a second contact layer located on a bottom surface of the second trench.

2 . The trench-type power device according to claim 1 , further comprising:
a well region located in the drift region; and a source region located in the well region, wherein the first trench and the second trench respectively penetrate through the source region and the well region and extend to a predetermined depth in the drift region.

3 . The trench-type power device according to claim 2 , wherein a dopant type of the semiconductor substrate, the drift region and the source region is N-type, a dopant type of the well region is P-type, and the semiconductor substrate serves as a drain region of a power transistor.

4 . The trench-type power device according to claim 2 , wherein the Schottky metal is located at a lower part of the side wall of the second trench and is in contact with the drift region, and a top end of the Schottky metal is located between the source region and the drift region.

5 . The trench-type power device according to claim 4 , further comprising:
a first contact layer located at an upper part of the side wall of the second trench and being in contact with the source region.

6 . The trench-type power device according to claim 5 , wherein the first contact layer and the second contact layer are made of metal silicide.

7 . The trench-type power device according to claim 2 , wherein:
an electrical connection path between the source region and the Schottky metal is provided via the conductive channel.

8 . The trench-type power device according to claim 1 , wherein the conductive material has a conductivity higher than that of the Schottky metal.

9 . A manufacturing method of a trench-type power device, comprising:
forming a drift region on a semiconductor substrate; forming a first trench and a second trench in the drift region; forming a gate stack in the first trench; forming Schottky metal on a side wall of the second trench; forming a doped region located below a bottom of the second trench, wherein a dopant type of the doped region is opposite to that of the drift region; forming a second contact layer located on a bottom surface of the second trench; and filling a conductive material in the second trench to form a conductive channel, wherein the Schottky metal and the drift region form a Schottky barrier diode, wherein the conductive channel is positionally separated from the drift region by the Schottky metal, which is different from the conductive material.

10 . The manufacturing method according to claim 9 , further comprising:
forming a well region in the drift region; and forming a source region in the well region, wherein the first trench and the second trench respectively penetrate through the source region and the well region and extend to a predetermined depth in the drift region.

11 . The manufacturing method according to claim 10 , wherein a dopant type of the semiconductor substrate, the drift region and the source region is N-type, a dopant type of the well region is P-type, and the semiconductor substrate serves as a drain region of a power transistor.

12 . The manufacturing method according to claim 10 , wherein the step of forming the Schottky metal comprises:
forming a conformal first metal layer in the second trench; and removing a portion, which is located at an upper part of the side wall of the second trench, of the first metal layer, and a portion, which is located at a bottom of the second trench, of the first metal layer, by performing anisotropic etching, wherein a portion, which remains at a lower part of the side wall of the second trench, of the first metal layer forms the Schottky metal.

13 . The manufacturing method according to claim 12 , wherein in the step of forming the Schottky metal, a top end of the Schottky metal is located between the source region and the drift region by controlling etching time of the anisotropic etching.

14 . The manufacturing method according to claim 12 , wherein after the step of forming the Schottky metal, the manufacturing method further comprises:
forming a conformal second metal layer in the second trench; generating silicide by reaction of a portion of the second metal layer, by performing a silicidation process; and removing unreacted metal of the second metal layer relative to the Schottky metal and the silicide, by performing a selective etching process, wherein a portion, which is located at the upper part of the side wall of the second trench, of the silicide, forms a first contact layer, and a portion, which is located at the bottom of the side wall of the second trench, of the silicide forms a second contact layer.

15 . The manufacturing method according to claim 12 , wherein an electrical connection path between the source region and the Schottky metal is provided by the conductive channel.

16 . The manufacturing method according to claim 10 , further comprising:
forming a P-type doped region below the bottom of the second trench by performing ion implantation via the second trench.

17 . The manufacturing method according to claim 9 , wherein the first contact layer and the second contact layer are made of metal silicide.

Assignees

• Hangzhou Silicon Magic Semiconductor Tech Co Ltd

Inventors

• Yang Xiao
• Chen Hui
• Wang Jiakun

Classifications

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title

• H10D62/158

  Dispositions · CPC title

• H10D62/154

  Dispositions · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title