Circuit board and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12538427-B2
Application number	US-202318474724-A
Country	US
Kind code	B2
Filing date	Sep 26, 2023
Priority date	Sep 26, 2023
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

A provided circuit board includes an embedded capacitor, a substrate, and an insulating layer. The embedded capacitor includes a dielectric layer, a first electrode and a second electrode. The dielectric layer has a first side surface, a second side surface adjacent to the first side surface, a third side surface opposite to the first side surface, and a fourth side surface opposite to the second side surface. The first and second electrodes respectively cover the first and third side surfaces. The substrate surrounds the embedded capacitor and is physically connected to the second and fourth side surfaces. The first electrode is between the first side surface and a sidewall of the substrate. The insulating layer covers the embedded capacitor and the substrate and extends from an upper surface to a lower surface of the substrate along the first electrode and the sidewall of the substrate.

First claim

What is claimed is:

1 . A circuit board, comprising:
a first embedded capacitor, comprising a dielectric layer, a first electrode and a second electrode, wherein the dielectric layer has a first side surface, a second side surface adjacent to the first side surface, a third side surface opposite to the first side surface, and a fourth side surface opposite to the second side surface, wherein the first electrode and the second electrode cover the first side surface and the third side surface respectively, wherein the first electrode comprises a first pad on the dielectric layer, a second pad beneath the dielectric layer, and an electrode plate physically connecting the first pad and the second pad; a substrate, surrounding the first embedded capacitor, wherein the substrate is physically connected to the second side surface and the fourth side surface of the dielectric layer, and the first electrode is located between the first side surface and a sidewall of the substrate; and an insulating layer, covering the first embedded capacitor and the substrate, wherein the insulating layer extends from an upper surface of the substrate to a lower surface of the substrate along the first electrode and the sidewall.

2 . The circuit board of claim 1 , wherein the substrate and the dielectric layer are integrally formed into one piece.

3 . The circuit board of claim 1 , wherein the dielectric layer has an upper surface connecting the first side surface and the second side surface, and the upper surface of the substrate and the upper surface of the dielectric layer are coplanar.

4 . The circuit board of claim 1 , further comprising a trace on the upper surface of the substrate, wherein the first pad and the trace have a same thickness.

5 . The circuit board of claim 1 , further comprising a contact located in the insulating layer and electrically connected to the first electrode, wherein an area of the first pad matches an area of the contact.

6 . The circuit board of claim 1 , wherein the first electrode comprises a first pad on the dielectric layer, the second electrode comprises a second pad on the dielectric layer, and the second pad and the first pad are separated from each other.

7 . The circuit board of claim 6 , wherein a total length of the first embedded capacitor is a sum of a length of the first pad, a length of the second pad and a distance between the first pad and the second pad.

8 . The circuit board of claim 1 , wherein opposite edges of the first electrode are respectively aligned with the second side surface and the fourth side surface of the dielectric layer.

9 . The circuit board of claim 1 , wherein the dielectric layer and the substrate are formed of a dielectric material comprising silicon, ceramics, glass, epoxy glass, graphene oxide, or a combination thereof.

10 . The circuit board of claim 1 , wherein the insulating layer fills between the first electrode and the sidewall of the substrate and fills between the second electrode and the substrate.

11 . The circuit board of claim 1 , further comprising a second embedded capacitor, wherein the second embedded capacitor comprises a dielectric layer, a third electrode and a fourth electrode, and a length of the dielectric layer of the second embedded capacitor between the third electrode and the fourth electrode is different from a length of the dielectric layer of the first embedded capacitor between the first electrode and the second electrode.

12 . The circuit board of claim 1 , further comprising a second embedded capacitor, wherein the second embedded capacitor comprises a dielectric layer and, a third electrode and a fourth electrode, and a pad area of the first electrode on the dielectric layer of the first embedded capacitor is different from a pad area of the third electrode on the dielectric layer of the second embedded capacitor.

13 . A method of manufacturing a circuit board, comprising:
providing an initial substrate; performing a first perforating process on the initial substrate to form a pair of openings, a dielectric layer between the pair of the openings, and a substrate physically connected to the dielectric layer, wherein the dielectric layer has a pair of side surfaces facing the pair of the openings and opposite to each other; forming a conductive layer on the substrate, on the dielectric layer and in the pair of the openings; forming a mask on the conductive layer, wherein the mask at least shields the pair of the openings; etching the conductive layer by using the mask to expose the dielectric layer and the substrate and remaining the conductive layer in the pair of the openings; after etching the conductive layer by using the mask, removing the mask; and after removing the mask, remaining a part of the conductive layer on the pair of the side surfaces of the dielectric layer and removing other part of the conductive layer outside the pair of the side surfaces in the pair of the openings.

14 . The method of claim 13 , wherein the step of forming the mask on the conductive layer comprises shielding a conductive portion of the conductive layer on the dielectric layer with the mask; and
wherein the step of remaining the conductive layer after removing the mask further comprising remaining the conductive portion on the dielectric layer.

15 . The method of claim 13 , wherein the step of removing the other part of the conductive layer outside the pair of the side surfaces in the pair of the openings comprises performing a second perforating process along the pair of the openings to expand the pair of the openings in a direction away from the pair of the side surfaces.

16 . The method of claim 15 , wherein same process steps are used in the first perforating process and the second perforating process.

17 . The method of claim 15 , wherein the step of forming the mask on the conductive layer comprises shielding a conductive portion of the conductive layer with the mask, the conductive portion being on a substrate portion of the substrate; and
wherein the step of performing the second perforating process comprises removing the conductive portion and the substrate portion.

18 . The method of claim 13 , wherein the step of forming the conductive layer in the pair of the openings comprises remaining a pair of voids in the pair of the openings; and
wherein the step of forming the mask on the conductive layer comprises remaining the pair of the voids in the pair of the openings.

19 . The method of claim 13 , further comprising forming an insulating layer on the dielectric layer and on the substrate, wherein the insulating layer is in physical contact with the dielectric layer and the substrate, and wherein the insulating layer extends into the pair of the openings to be in physical contact with the conductive layer on the pair of the side surfaces.

Assignees

• Hongqisheng Prec Electronics Qinhuangdao Co Ltd
• Avary Holding Shenzhen Co Ltd
• Garuda Tech Co Ltd

Inventors

• Huang xiao-long
• Men Yu-Jia

Classifications

• H05K2203/0186

  Mask formed or laid on PCB, the mask having recesses or openings specially designed for mounting components or body parts thereof · CPC title

• H05K2201/09227

  Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting · CPC title

• H05K2201/0183

  Dielectric layers · CPC title

• H05K1/16

  incorporating printed electric components, e.g. printed resistors, capacitors or inductors · CPC title

• H05K1/111

  Pads for surface mounting, e.g. lay-out · CPC title