Filter including at least one inductor-capacitor structure formed in a multi-layer substrate and method for manufacturing the filter

Patent metadata

Field	Value
Publication number	US-12537498-B2
Application number	US-202218027211-A
Country	US
Kind code	B2
Filing date	Jun 24, 2022
Priority date	Jun 24, 2022
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

A filter and a method for manufacturing a filter are provided and belong to the field of electronics technology. The method includes forming at least one inductor and at least one capacitor. Forming the at least one inductor includes: providing a first dielectric substrate; the first dielectric substrate includes a first surface and a second surface opposite to each other along a thickness direction thereof; forming first sub-structures of the inductor on the first surface; forming first connection vias penetrating through the first dielectric substrate in the thickness direction thereof; forming first connection electrodes in the first connection vias; and forming second sub-structures of the inductor on the second surface; the first connection electrodes sequentially connects the first and second sub-structures through the first connection vias to form a coil structure of the inductor.

First claim

What is claimed is:

1 . A method for manufacturing a filter, comprising forming at least one inductor and at least one capacitor; wherein the forming the at least one inductor comprises:
providing a first dielectric substrate; wherein the first dielectric substrate comprises a first surface and a second surface opposite to each other along a thickness direction of the first dielectric substrate; forming first sub-structures of each of the at least one inductor on the first surface of the first dielectric substrate; forming first connection vias penetrating through the first dielectric substrate in the thickness direction of the first dielectric substrate; forming first connection electrodes in the first connection vias; and forming second sub-structures of the at least one inductor on the second surface of the first dielectric substrate; wherein the first connection electrodes sequentially connects the first sub-structures and the second sub-structures through the first connection vias to form a coil structure of the at least one inductor, wherein a first plate of each of the at least one capacitor is formed while forming the first sub-structures of the at least one inductor, wherein the method further comprises: forming a first interlayer dielectric layer on a side of the first sub-structures of the at least one inductor and the first plate of the at least one capacitor away from the first dielectric substrate; and forming a pattern comprising a second plate of the at least one capacitor on a side of the first interlayer dielectric layer away from the first dielectric substrate through a patterning process.

2 . The method according to claim 1 , wherein the first dielectric substrate is processed by any one of a sand blast method, a photosensitive glass method, a focus discharge method, a plasma etching method, a laser ablation method, an electrochemical method or a laser induced etching method to form the first connection vias.

3 . The method according to claim 1 , wherein the forming the first connection electrodes in the first connection vias comprises:
forming a first conductive film layer in the first connection vias as a first seed layer; and electroplating the first seed layer to form the first connection electrodes filled in the first connection vias.

4 . The method according to claim 3 , wherein the first seed layer covers the second surface of the first dielectric substrate; and after the electroplating the first seed layer to form the first connection electrodes filled in the first connection vias, the method further comprises:
patterning the electroplated first seed layer on the second surface to form the second sub-structures.

5 . The method according to claim 1 , wherein the forming the first connection electrodes in the first connection vias comprises:
forming a first conductive film layer in the first connection vias as a first seed layer; and electroplating the first seed layer to form the first connection electrodes covering inner walls of the first connection vias; wherein the first connection electrodes cover the inner walls of the first connection vias to define first accommodation spaces.

6 . The method according to claim 5 , wherein before the forming second sub-structures of the at least one inductor on the second surface of the first dielectric substrate, the method further comprises:
forming filling structures to fill the first accommodation spaces, respectively.

7 . The method according to claim 5 , wherein the first seed layer covers the second surface of the first dielectric substrate; and after the electroplating the first seed layer to form the first connection electrodes filled in the first connection vias, the method further comprises:
patterning the electroplated first seed layer on the second surface to form the second sub-structures.

8 . The method according to claim 1 , wherein the forming the second sub-structures of the at least one inductor on the second surface of the first dielectric substrate comprises:
forming a second conductive film layer on the second surface of the first dielectric substrate as a second seed layer; electroplating the second seed layer to increase a thickness of the second conductive film layer; and patterning the electroplated second seed layer to form the second sub-structures.

9 . The method according to claim 1 , wherein the forming the first sub-structures of the at least one inductor on the first surface of the first dielectric substrate comprises:
sequentially depositing a first film layer, a second film layer and a third film layer on the first surface of the first dielectric substrate, and forming the first sub-structures through a patterning process such that the first sub-structure comprises a first portion, a second portion and a third portion stacked sequentially.

10 . The method according to claim 1 , wherein a distance between every two adjacent first connection vias is not less than twice a diameter of each first connection via.

11 . The method according to claim 1 , wherein the forming the pattern comprising the second plate of the at least one capacitor on a side of the first interlayer dielectric layer away from the first dielectric substrate through the patterning process comprises:
sequentially depositing a fourth film layer, a fifth film layer and a sixth film layer on a side of the first interlayer dielectric layer away from the first dielectric substrate, and forming the second plate of the at least one capacitor through the patterning process such that the second plate comprises a seventh portion, an eighth portion and a ninth portion stacked sequentially.

12 . The method according to claim 1 , further comprising:
forming a second interlayer dielectric layer on a side of the second plate of the at least one capacitor away from the first dielectric substrate, and forming a second connection via penetrating through the first interlayer dielectric layer and the second interlayer dielectric layer and a third connection via penetrating through the second interlayer dielectric layer; and forming a second connection electrode and a third connection electrode on a side of the second interlayer dielectric layer away from the first dielectric substrate, through a patterning process; wherein the second connection electrode is connected to a lead terminal of the at least one inductor through the second connection via, and the third connection electrode is electrically connected to the second plate of the at least one capacitor through the third connection via.

13 . The method according to claim 12 , further comprising:
sequentially forming a first protective layer and a first planarization layer on a side of the second connection electrode and the third connection electrode away from the first dielectric substrate; forming a fourth connection via and a fifth connection via penetrating through the first protective layer and the first planarization layer; and forming a first connection pad and a second connection pad; wherein the first connection pad is connected to the second connection electrode through the fourth connection via, and the second connection pad is connected to the third connection electrode through the fifth connection via.

14 . The method according to claim 13 , wherein the first planarization layer, the fourth connection via, the fifth connection via, the first connection pad, and the second connection pad are all formed after the second sub-structures of the at least one inductor are formed.

15 . The method according to claim 1 , further comprising:
sequentiall

Assignees

• Beijing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• An Qichang
• Xiao Yuelei
• Li Yue
• Wu Yifan
• Han Kidong
• Cao Xue
• Chang Wenbo
• Li Huiying
• Wang Lihui
• Ren Yanfei
• Wei Qiuxu
• Feng Yulin
• Li Biqi

Classifications

• H03H2001/0085

  Multilayer, e.g. LTCC, HTCC, green sheets · CPC title

• H03H7/0115 Primary

  comprising only inductors and capacitors (H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence) · CPC title

• H03H7/09

  Filters comprising mutual inductance · CPC title