Switch control method to suppress the effect of even order harmonics in supply voltage on ASD

Patent metadata

Field	Value
Publication number	US-12537440-B2
Application number	US-202217958771-A
Country	US
Kind code	B2
Filing date	Oct 3, 2022
Priority date	Oct 4, 2021
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

The invention discloses systems ( 100 ) and methods ( 200, 300 ) for reducing the effect of even-order harmonics in supply voltage on the DC side components in AC-DC converters having any kind of controlled power electronic switches or their combinations. The method involves modifying the time of firing the various switches ( 112, 114 ) through a control logic arrives at through either measuring or estimating the DC bus voltage or the input AC voltage. The proposed control methods are useful in ASDs where full bridge configuration is used for AC to DC conversion. The proposed control may also be used in ASDs where a half bridge rectifier system is used. The proposed method reduces the stress on the DC bus capacitor and increases the lifetime of the capacitor. It further reduces the peak current through the device, which reduces stress on the rectifier components. It also reduces the Total Harmonic Distortion (THD i ) of the line current.

First claim

The invention claimed is:

1 . A control method of operating a controlled bridge rectifier in a system with an input controlled bridge rectifier circuit with upper leg semiconductor switches and lower leg semiconductor switches, a DC bus capacitor, and one or more controllers, the method comprising:
estimating a measure of even ordered harmonics present in a supply voltage; triggering the upper leg switches and the lower leg switches at different predetermined angles by the one or more controllers based on the estimated measure when the estimated measure is greater than a pre-set threshold voltage magnitude; and suppressing the effects of even order harmonics present in the supply voltage on the DC bus capacitor; wherein estimating the measure of even ordered harmonics present in the supply voltage comprises obtaining the magnitude and phase angle of the voltage (Vdc) measured across the DC bus at a frequency component that is thrice a supply frequency component.

2 . The method as claimed in claim 1 , wherein the method comprises:
triggering the upper leg switches at a first predetermined angle and the lower leg switches at a second predetermined angle if the magnitude is greater than the pre-set threshold magnitude and if the phase angle is less than a threshold angle; or triggering the upper leg switches at the second predetermined angle and the lower leg switches at the first predetermined angle if the magnitude is greater than the pre-set threshold magnitude and if the phase angle is greater than the threshold angle.

3 . The method as claimed in claim 2 , wherein the pre-set threshold magnitude is a function of a resultant capacitor ripple current.

4 . The method as claimed in claim 2 , wherein the first predetermined angle is in a range 0° to 45°.

5 . The method as claimed in claim 2 , wherein the second predetermined angle is in a range 0° to 45°.

6 . A control method of operating a controlled bridge rectifier in a system with an input controlled bridge rectifier circuit with upper leg semiconductor switches and lower leg semiconductor switches, a DC bus capacitor, and one or more controllers, the method comprising:
estimating a measure of even ordered harmonics present in a supply voltage; triggering the upper leg switches and the lower leg switches at different predetermined angles by the one or more controllers based on the estimated measure when the estimated measure is greater than a pre-set threshold voltage magnitude; and suppressing the effects of even order harmonics present in the supply voltage on the DC bus capacitor; wherein estimating the measure of even ordered harmonics present in the supply voltage (v line ) comprises calculating an asymmetry factor (AF) value of the supply voltage using

AF
=

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❘
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V

pos
⁢
_
⁢
peak

❘
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-

❘
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V

neg
⁢
_
⁢
peak

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V
rms

wherein V pos_peak is the positive peak voltage, V neg_peak is the negative peak voltage and V rms is the root mean square value of the supply voltage.

7 . The method as claimed in claim 6 , wherein the method comprises:
triggering the upper leg switches at the first predetermined angle and the lower leg switches at the second predetermined angle if the AF is less than the pre-set threshold magnitude and if an average value of a Zero Cross Detector (ZCD) is less than a first ZCD threshold value; or triggering the upper leg switches at the second predetermined angle and the lower leg switches at the first predetermined angle if the AF is less than the pre-set threshold magnitude and if the average value of the ZCD is more than a second ZCD threshold value.

8 . The method as claimed in claim 6 , wherein the method comprises:
triggering the upper leg switches at a first predetermined angle and the lower leg switches at a second predetermined angle if the AF is more than the pre-set threshold magnitude, and a positive peak value of v line is more than an absolute value of a negative peak value of v line ; or triggering the upper leg switches at the second predetermined angle and the lower leg switches at the first predetermined angle if the AF is more than the pre-set threshold magnitude, and the positive peak value of v line is less than the absolute value of the negative peak of v line .

9 . The method as claimed in claim 8 , wherein the first predetermined angle is in a range 0° to 45°.

10 . The method as claimed in claim 8 , wherein the second predetermined angle is in a range 0° to 45°.

11 . The method as claimed in claim 8 , wherein the AF threshold is below a protection threshold required to protect the DC bus capacitor.

12 . The method as claimed in claim 8 , wherein the first ZCD threshold is above a protection threshold required to protect the DC bus capacitor.

13 . The method as claimed in claim 8 , wherein the second ZCD threshold is below a protection threshold required to protect the DC bus capacitor.

14 . A control method of operating a controlled bridge rectifier in a system with an input controlled bridge rectifier circuit with upper leg semiconductor switches and lower leg semiconductor switches, a DC bus capacitor, and one or more controllers, the method comprising:
estimating a measure of even ordered harmonics present in a supply voltage; wherein estimating the measure of even ordered harmonics present in the supply voltage (v line ) comprises calculating an asymmetry factor (AF) value of the supply voltage using

AF
=

❘
"\[LeftBracketingBar]"

❘
"\[LeftBracketingBar]"

V

pos
⁢
_

Assignees

• Indian Inst Tech Madras
• Danfoss Power Electronics As
• Indian Institute Of Tech Madras

Inventors

• Gopalan Seshadri
• Kumar Dinesh
• Vasudevan Krishna

Classifications

• H02M7/1626

  with automatic control of the output voltage or current · CPC title

• H02M1/083

  for the ignition at the zero crossing of the voltage or the current · CPC title

• H02M1/12 Primary

  Arrangements for reducing harmonics from AC input or output · CPC title

• H02M1/0012

  Control circuits using digital or numerical techniques (in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873) · CPC title

• H02M7/2195

  the switches being synchronously commutated at the same frequency of the AC input voltage · CPC title