Single control signal generation in power stage controller

Patent metadata

Field	Value
Publication number	US-12537437-B2
Application number	US-202318454399-A
Country	US
Kind code	B2
Filing date	Aug 23, 2023
Priority date	Aug 23, 2023
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

A controller for controlling a power stage having one or more phases is presented. The controller includes a reference circuit that generates a reference signal; a ramp generator generating a feedback ramp signal based on a feedback signal of the power stage; and a modulator generating a control signal for controlling at least one phase of the power stage. The control signal may include a series of pulses in which each pulse is associated with a corresponding phase of the power stage.

First claim

The invention claimed is:

1 . A controller for controlling a power stage having one or more phases, the controller comprising:
a reference circuit adapted to generate a reference signal; a ramp generator adapted to generate a feedback ramp signal based on a feedback signal of the power stage; and a modulator adapted to generate a control signal for controlling at least one phase of the power stage, wherein the modulator comprises:
a comparator adapted to compare the feedback ramp signal with the reference signal to obtain a modulation signal;
a sampling circuit configured to sample the modulation signal and to generate a digital modulation signal;
a logic circuit configured to generate the control signal based on the digital modulation signal; and
an oscillator coupled to the sampling circuit and the logic circuit.

2 . The controller as claimed in claim 1 , wherein the feedback ramp signal has a frequency that is function of number of active phases of the power stage.

3 . The controller as claimed in claim 1 , wherein the control signal comprises a series of pulses, each pulse being associated with a corresponding phase of the power stage.

4 . The controller as claimed in claim 3 , wherein each pulse is associated with an on time of the corresponding phase.

5 . The controller as claimed in claim 1 , wherein the logic circuit comprises a counter configured to calculate a duration between successive pulses of the control signal.

6 . The controller as claimed in claim 1 , wherein the logic circuit is configured to encode the digital modulation signal for a specific protocol.

7 . The controller as claimed in claim 1 , wherein the logic circuit is a state machine.

8 . The controller as claimed in claim 1 , wherein the ramp generator comprises:
a capacitor; a first transconductance amplifier coupled to the capacitor via a first switch; a second transconductance amplifier coupled to the capacitor via a second switch; and a timer configured to control the first and second switches.

9 . The controller as claimed in claim 8 , comprising a closed loop operational amplifier.

10 . The controller as claimed in claim 1 , further comprising a duty cycle estimator configured to estimate a duty cycle of the power stage and a ramp amplitude adjuster configured to adjust an amplitude of the feedback ramp signal based on the estimated duty cycle.

11 . A power supply comprising the controller and the power stage as claimed in claim 1 .

12 . The power supply as claimed in claim 11 , wherein the controller is coupled to the power stage via a single wire interface.

13 . The power supply as claimed in claim 11 , wherein the power stage comprises a plurality of phases, each phase comprising a high side power switch coupled to a low side power switch at a switching node.

14 . The power supply as claimed in claim 13 , wherein each phase the power stage comprises a driver, and wherein the driver comprises a decoder for decoding the control signal.

15 . The power supply as claimed in claim 14 , wherein the decoder is configured to measure a pulse width of each pulse of the control signal and compare the measured pulse width with a predefined pulse width value.

16 . The power supply as claimed in claim 11 , wherein the power supply is a constant on time converter.

17 . A method of controlling a power stage having one or more phases, the method comprising:
generating a reference signal; generating a feedback ramp signal based on a feedback signal of the power stage; comparing the feedback ramp signal with the reference signal to obtain a modulation signal; sampling, according to a clock signal provided by an oscillator, the modulation signal to generate a digital modulation signal; and generating, based on the digital modulation signal and according to the clock signal provided by the oscillator, a control signal for controlling at least one phase of the power stage.

18 . The method as claimed in claim 17 , wherein the control signal is a single control signal.

19 . The method as claimed in claim 17 , comprising:
calculating a duration between successive pulses of the control signal; and activating one or more phases if the duration is less than a first threshold value; or deactivating one or more phases if the duration is more than a second threshold.

Assignees

• Renesas Electronics Corp

Inventors

• Labbe Benoit
• Bumgarner Adam Matthew
• Lalithambika Vinod Aravindakshan
• Warrington Allan Richard

Classifications

• H02M1/0025

  Arrangements for modifying reference values, feedback values or error values in the control loop of a converter · CPC title

• H02M1/0009

  Devices or circuits for detecting current in a converter · CPC title

• H02M1/082 Primary

  with digital control · CPC title

• H02M3/155

  using semiconductor devices only · CPC title

• H02M1/0096

  Means for increasing hold-up time, i.e. the duration of time that a converter's output will remain within regulated limits following a loss of input power · CPC title